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參數(shù)資料
| 型號： | CY2412-1 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MPEG Clock Generator with VCXO |
| 中文描述： | 的MPEG時鐘發(fā)生器，石英振蕩器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 128K |
| 代理商： | CY2412-1 |
CY2412
Document #: 38-07227 Rev. *D
Page 3 of 6
Absolute Maximum Conditions
Recommended Operating Conditions
DC Electrical Characteristics
AC Electrical Characteristics
Parameter
V
DD
T
S
T
J
Description
Min.
–0.5
–65
–
Max.
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
°C
°C
V
V
kV
Supply Voltage
Storage Temperature
[3]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electrostatic Discharge
V
SS
– 0.3
V
SS
– 0.3
2
Parameter
Description
Min.
3.14
0
Typ.
3.3
Max.
3.47
70
15
Unit
V
°C
pF
MHz
ms
V
DD
T
A
C
LOAD
f
REF
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
Power-up time for all VDDs to reach
minimum specified voltage (power
ramps must be monotonic)
13.5
0.05
500
Parameter
I
OH
I
OL
C
IN
I
IZ
f
XO
V
VCXO
f
VBW
I
DD
Description
Test Conditions
Min.
12
12
Typ.
24
24
Max.
Unit
mA
mA
pF
μ
A
ppm
V
kHz
mA
Output High Current
Output Low Current
Input Capacitance
Input Leakage Current
VCXO pullability range
VCXO input range
VCXO input bandwidth
Supply Current
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
7
5
+150
0
V
DD
DC to 200
Sum of Core and Output Current
35
Parameter
[4]
DC
ER
Description
Output Duty Cycle
Rising Edge Rate
Test Conditions
Min.
45
0.8
Typ.
50
1.4
Max.
55
Unit
%
V/ns
Duty Cycle is defined in
Figure 1
, 50% of V
DD
Clock Edge Rate, Measured from 20% to 80%
of V
DD,
C
LOAD
= 15 pF. See
Figure 2
.
Output Clock Edge Rate, Measured from 80% to
20% of V
DD,
C
LOAD
= 15 pF. See
Figure 2
.
Peak to Peak period jitter
EF
Falling Edge Rate
0.8
1.4
V/ns
t
9
t
10
Clock Jitter
PLL Lock Time
100
200
3
ps
ms
Notes:
2. Float X
if X
is externally driven.
3. Rated for ten years.
4. Not 100% tested.
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