參數(shù)資料
型號: CY2318ANZPVC-11
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs
中文描述: 2318 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: SSOP-48
文件頁數(shù): 3/9頁
文件大?。?/td> 184K
代理商: CY2318ANZPVC-11
CY2318ANZ
Document #: 38-07181 Rev. *B
Page 3 of 9
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to “0”.
Serial interface address for the CY2318ANZ is:
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0:SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7 18
SDRAM7 (Active/Inactive)
Bit 6 17
SDRAM6 (Active/Inactive)
Bit 5 14
SDRAM5 (Active/Inactive)
Bit 4 13
SDRAM4 (Active/Inactive)
Bit 3 9
SDRAM3 (Active/Inactive)
Bit 2 8
SDRAM2 (Active/Inactive)
Bit 1 5
SDRAM1 (Active/Inactive)
Bit 0 4
SDRAM0 (Active/Inactive)
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
45
SDRAM15 (Active/Inactive)
Bit 6
44
SDRAM14 (Active/Inactive)
Bit 5
41
SDRAM13 (Active/Inactive)
Bit 4
40
SDRAM12 (Active/Inactive)
Bit 3
36
SDRAM11 (Active/Inactive)
Bit 2
35
SDRAM10 (Active/Inactive)
Bit 1
32
SDRAM9 (Active/Inactive)
Bit 0
31
SDRAM8 (Active/Inactive)
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
28
SDRAM17 (Active/Inactive)
Bit 6
21
SDRAM16 (Active/Inactive)
Bit 5
--
Reserved, drive to 0
Bit 4
--
Reserved, drive to 0
Bit 3
--
Reserved, drive to 0
Bit 2
--
Reserved, drive to 0
Bit 1
--
Reserved, drive to 0
Bit 0
--
Reserved, drive to 0
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