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參數(shù)資料
| 型號： | CY23EP09 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer(2.5V或3.3V,10-220 MHz,低抖動, 9輸出零延遲緩沖器) |
| 中文描述： | 2.5V或3.3V，10-220兆赫，低抖動，9輸出零延遲緩沖器電壓（2.5V或3.3V的,10 - 220頻率，低抖動，9輸出零延遲緩沖器） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 359K |
| 代理商： | CY23EP09 |
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output
Zero Delay Buffer
CY23EP09
Cypress Semiconductor Corporation
Document #: 38-07760 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised October 5, 2005
Features
10 MHz to 220 MHz maximum operating range
Zero input-output propagation delay, adjustable by
loading on CLKOUT pin
Multiple low-skew outputs
— 45 ps typical output-output skew
— One input drives nine outputs, grouped as 4 + 4 + 1
25 ps typical cycle-to-cycle jitter
15 ps typical period jitter
Standard and High drive strength options
Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages
3.3V or 2.5V operation
Industrial temperature available
Functional Description
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed
to distribute high-speed clocks and is available in a 16-pin
SOIC or TSSOP package. The -1H version operates up to 220
(200) MHz frequencies at 3.3V (2.5V), and has higher drive
than the -1 devices. All parts have on-chip PLLs that lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25
μ
A of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed
and REF is output from DC to the maximum allowable
frequency. The part behaves like a non-zero delay buffer in this
mode, and the outputs are not tri-stated.
The CY23EP09 is available in different configurations, as
shown in the Ordering Information table. The CY23EP09-1 is
the base part. The CY23EP09-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Top View
Pin Configuration
PLL
MUX
Select Input
Decoding
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
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| CY23FP12OXIT | 200-MHz Field Programmable Zero Delay Buffer |
| CY23FP12OC | Coaxial Cable; Coaxial RG/U Type:59; Impedance:75ohm; Conductor Size AWG:20; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Capacitance:16.2pF/ft; Conductor Material:Steel; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CY23FP12OCT | Belden RG-59/U Coaxial Cable, Wire Size: 20 AWG, Color: Black, Length: 1000 feet, Conductor Material: Bare Copper, Shielding: 40 % Aluminum Braid, Jacket: PVC |
| CY23FP12OI | Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Conductor Material:Copper; Jacket Color:Black; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| CY23FP12OIT | Coaxial Cable; Coaxial RG/U Type:11; Impedance:75ohm; Conductor Size AWG:14; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Conductor Material:Copper; Jacket Color:Black; Leaded Process Compatible:Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23EP09_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer |
| CY23EP09SXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY23EP09SXC-1 | 功能描述:鎖相環(huán) - PLL 3.3VZDB COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23EP09SXC-1H | 功能描述:鎖相環(huán) - PLL 2.5V 3.3V 10-220 MHz Zero Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23EP09SXC-1HT | 功能描述:鎖相環(huán) - PLL 3.3VZDB COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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