參數(shù)資料
型號(hào): CY2318ANZOXC-11T
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs
中文描述: 2318 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: LEAD FREE, SSOP-48
文件頁數(shù): 5/9頁
文件大小: 184K
代理商: CY2318ANZOXC-11T
CY2318ANZ
Document #: 38-07181 Rev. *B
Page 5 of 9
Switching Characteristics
[4]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
Maximum Operating Frequency
Duty Cycle
[3, 5]
= t
2
÷
t
1
Rising Edge Rate
[3]
Falling Edge Rate
[3]
Output to Output Skew
[3]
SDRAM Buffer LH Prop. Delay
[3]
SDRAM Buffer HL Prop. Delay
[3]
SDRAM Buffer Enable Delay
[3]
SDRAM Buffer Disable Delay
[3]
100
MHz
Measured at 1.5V
45.0
50.0
55.0
%
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Measured between 0.4V and 2.4V
0.9
1.5
4.0
V/ns
Measured between 2.4V and 0.4V
0.9
1.5
4.0
V/ns
All outputs equally loaded
150
250
ps
Input edge greater than 1 V/ns
1.0
3.5
5.0
ns
Input edge greater than 1 V/ns
1.0
3.5
5.0
ns
Input edge greater than 1 V/ns
1.0
5
12
ns
Input edge greater than 1 V/ns
1.0
20
30
ns
Switching Waveforms
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Duty Cycle Timing
t
1
t
2
1.5V
1.5V
1.5V
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t
4
Output-Output Skew
1.5V
t
5
OUTPUT
OUTPUT
1.5V
相關(guān)PDF資料
PDF描述
CY2318ANZPVC-11 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs
CY2318ANZPVC-11T 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs
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