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參數(shù)資料
| 型號(hào)： | CY23020-3 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | CY23020-3 |
10-output, 400-MHz LVPECL Zero Delay Buffer
CY23020-3
Cypress Semiconductor Corporation
Document #: 38-07473 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised June 5, 2003
Features
400-ps max Total Timing Budget
(TTB
) window
10 LVPECL outputs
1 LVPECL differential input
Selectable output frequency range from 100 to 400 MHz
Multiply by 2 option
15-ps RMS Cycle-Cycle Jitter
Power-down mode
Lock indicator
3.3V power supply
Available in 48-pin QFN package
Overview
TheCY23020-3 is a high-performance 400-MHz LVPECL
Output phase-locked loop (PLL)-based zero delay buffer
(ZDB) designed for high- speed clock distribution applications.
The device features a guaranteed TTB window specifying all
occurrences of output clocks with respect to the input
reference clock across variations in voltage, temperature,
process, frequency, and ramp rate.
Additionally, the CY23020-3 can be used as a fan-out buffer
via the S[1:2] control pins. In this mode, the PLL is bypassed
and the reference clock is routed to the output buffers.
Block Diagram
Pin Configurations
CY23020-3
48
F
B
O
U
T
+
47
46
45
F
B
I
N
-
44
N
C
43
L
O
C
K
42
V
D
D
C
41
G
N
D
C
40
R
E
F
-
39
R
E
F
+
38
V
D
D
37
Q
9
+
13
14
15
16
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
V
D
D
F
B
I
N
+
Q
4
-
G
N
D
S
2
S
1
M
U
L
R
A
N
G
E
G
N
D
C
V
D
D
C
V
D
D
C
G
N
D
C
G
N
D
Q
5
-
FBOUT-
GND
Q1-
Q1+
VDD
Q2+
Q2-
GND
Q3-
Q3+
VDD
Q4+
Q9-
GND
Q8-
Q8+
VDD
Q7+
Q7-
GND
Q6-
Q6+
VDD
Q5+
Q1+
Q1-
Q3+
Q3-
Q2+
Q2-
Q4+
Q4-
Q5+
Q4-
Q6+
Q6-
Q7+
Q8+
Q9+
FBOUT+
FBOUT-
PLL
Control
Logic
FBIN-
FBIN+
S1:2
RANGE
MUL
REF-
REF+
÷
1/
÷
2
÷
1
÷
2
LOCK
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PDF描述 |
|---|---|
| CY2308ZC-1HT | Eight Distributed-Output Clock Driver |
| CY2308ZC-5 | Eight Distributed-Output Clock Driver |
| CY2308ZI-5 | Eight Distributed-Output Clock Driver |
| CY2303 | Clocks and Buffers |
| CY2303SC | THREE DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|8PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23020LFI-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY23020LFI-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:20-output, 200-MHz Zero Delay Buffer |
| CY23020LFI-3 | 功能描述:鎖相環(huán) - PLL 400MHz IND Zero Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23020LFI-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:10-output, 400-MHz LVPECL Zero Delay Buffer |
| CY23020ZC-1 | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:10-OUTPUT,400MHZ LVPECL ZERO DELAY BUFFER - Bulk |
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