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| 型號(hào)： | CY2302-01SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Frequency Multiplier and Zero Delay Buffer |
| 中文描述： | 2302 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | CY2302-01SI |
CY2302
Document #: 38-07154 Rev. **
Page 3 of 7
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a de-
signer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be implemented by either mak-
ing the trace to the FBIN pin a little shorter or a little longer than
the traces to the devices being clocked.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals to the signal coming from
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) that is
put into the feedback path.
Referring to
Figure 2
, if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay from the ZDB output to the ASIC/Buffer output must be
accounted for.
Reference
Signal
Feedback
Input
ASIC/
Buffer
Zero
Delay
Buffer
A
Figure 2. Six Output Buffer in the Feedback Path
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23020-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY23020LFI-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY23020LFI-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:20-output, 200-MHz Zero Delay Buffer |
| CY23020LFI-3 | 功能描述:鎖相環(huán) - PLL 400MHz IND Zero Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23020LFI-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:10-output, 400-MHz LVPECL Zero Delay Buffer |
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