- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378480 > CY2302-01SI (CYPRESS SEMICONDUCTOR CORP) Frequency Multiplier and Zero Delay Buffer PDF資料下載
參數(shù)資料
| 型號(hào)： | CY2302-01SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Frequency Multiplier and Zero Delay Buffer |
| 中文描述： | 2302 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | CY2302-01SI |
CY2302
Document #: 38-07154 Rev. **
Page 2 of 7
Overview
The CY2302 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing max-
imum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
“
How to Implement Zero Delay,
”
and
“
Inserting Other Devices
in Feedback Path.
”
The CY2302 is a pin-compatible upgrade of the Cypress
W42C70-01. The CY2302 addresses some application de-
pendent problems experienced by users of the older device.
Pin Definitions
Pin Name
IN
FBIN
Pin No.
2
1
Pin
Type
I
I
Pin Description
Reference Input:
The output signals will be synchronized to this signal.
Feedback Input:
This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the REF signal input (IN).
Output 1:
The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see
Table 1
).
Output 2:
The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See
Table 1
.
Power Connections:
Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-
μ
F
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance.
Ground Connection:
Connect all grounds to the common system ground plane.
Function Select Inputs:
Tie to V
DD
(HIGH, 1) or GND (LOW, 0) as desired per
Table 1
.
OUT1
6
O
OUT2
8
O
VDD
7
P
GND
FS0:1
3
P
I
4, 5
C8
G
Ferrite
Bead
Power Supply Connection
V+
G
C
A
G
FS1
FS0
GND
IN
FBIN
10 μF
0.01 μF
1
2
3
4
8
7
6
5
22
22
G
C9 = 0.1 μF
OUTPUT 1
OUTPUT 2
OUT 2
V
DD
OUT 1
Figure 1. Schematic/Suggested Layout
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2313ANZ | 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs(帶3 DIMM的應(yīng)用于桌上電腦PC 的3.3V 13輸出SDRAM緩沖器) |
| CY2318ANZ | 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs |
| CY2318ANZOXC-11 | 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs |
| CY2318ANZOXC-11T | 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs |
| CY2318ANZPVC-11 | 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23020-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY23020LFI-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY23020LFI-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:20-output, 200-MHz Zero Delay Buffer |
| CY23020LFI-3 | 功能描述:鎖相環(huán) - PLL 400MHz IND Zero Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23020LFI-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:10-output, 400-MHz LVPECL Zero Delay Buffer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。