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參數(shù)資料
| 型號： | CY2300 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Phase-Aligned Clock Multiplier |
| 中文描述： | 相不結(jié)盟時鐘倍頻 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 125K |
| 代理商： | CY2300 |
CY2300
Document #: 38-07252 Rev. *B
Page 2 of 7
Functional Description
The CY2300 is a 4-output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN
output frequencies on respective output pins.
The part has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The input-to-output skew is guar-
anteed to be less than
±
200 ps, and output-to-output skew is
guaranteed to be less than 200 ps.
Multiple CY2300 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
Operating Conditions for CY2300SC Commercial Temperature Devices
The CY2300 is available in commercial and industrial temper-
ature ranges.
Maximum Ratings
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage (Except Ref) ..............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF........................................... –0.5 to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature.................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............................>2000V
Pin Definitions
Pin
Signal
[1]
Description
1
1/2xREF
Clock output, 1/2x Reference
2
GND
Ground
3
REFIN
Input Reference frequency, 5V tolerant input
4
REF
Clock output Reference
5
REF
Clock output Reference
6
2xREF
Clock output, 2x Reference
7
VDD
3.3V Supply
8
OE
Output Enable (weak pull-up)
Parameter
Description
Min.
Max.
Unit
V
DD
T
A
C
L
Supply Voltage
3.0
3.6
V
Operating Temperature (Ambient Temperature)
0
70
°C
Load Capacitance, Fout < 133.33 MHz
18
pF
Load Capacitance,133.33 MHz < Fout < 166.67 MHz
12
pF
C
IN
Input Capacitance
7
pF
t
PU
Electrical Characteristics for CY2300SC Commercial Temperature Devices
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Min.
Max.
0.8
Unit
V
V
μ
A
μ
A
V
V
mA
mA
mA
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
[2]
Output HIGH Voltage
[2]
Supply Current
2.0
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA
I
OH
= –8 mA
Unloaded outputs, REFIN = 66 MHz
Unloaded outputs, REFIN = 33 MHz
Unloaded outputs, REFIN = 20 MHz
100
50
0.4
2.4
45
32
18
Notes:
1.
2.
Weak pull-down on all outputs.
Parameter is guaranteed by design and characterization. It is not 100% tested in production.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2300SC | Phase-Aligned Clock Multiplier |
| CY2300SI | Phase-Aligned Clock Multiplier |
| CY2302-01SC | Frequency Multiplier and Zero Delay Buffer |
| CY2302 | CONN MINI D RECPT 68POS VERT T/H |
| CY2302-01SI | Frequency Multiplier and Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2300_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Phase-Aligned Clock Multiplier |
| CY2300_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Phase-Aligned Clock Multiplier |
| CY2300ESXC | 制造商:Cypress Semiconductor 功能描述: |
| CY2300SC | 制造商:Cypress Semiconductor 功能描述:PLL Clock Multiplier Single 10MHz to 166.67MHz 8-Pin SOIC 制造商:Rochester Electronics LLC 功能描述:CLOCK DRIVER - Bulk |
| CY2300SCT | 制造商:Cypress Semiconductor 功能描述:PLL Clock Multiplier Single 10MHz to 166.67MHz 8-Pin SOIC T/R |
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