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參數(shù)資料
| 型號： | CY2292SXL-XXXT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| 中文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, MS-012, SOIC-16 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 189K |
| 代理商： | CY2292SXL-XXXT |
CY2292
Document #: 38-07449 Rev. *B
Page 8 of 11
t
9A
Clock Jitter
[14]
Peak-to-peak period jitter (t
9A
max. – t
9A
min.),
% of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.)
(4 MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter
(16 MHz < f
OUT
<
50 MHz)
Peak-to-peak period jitter
(f
OUT
> 50 MHz)
Lock Time from Power-up
< 0.5
1
%
t
9B
Clock Jitter
[14]
< 0.7
1
ns
t
9C
Clock Jitter
[14]
< 400
500
ps
t
9D
Clock Jitter
[14]
< 250
350
ps
t
10A
Lock Time for
CPLL
Lock Time for
UPLL and SPLL
Slew Limits
< 25
50
ms
t
10B
Lock Time from Power-up
< 0.25
1
ms
CPU PLL Slew Limits
CY2292I
CY2292FI
20
20
66.6
60
MHz
MHz
Switching Waveforms
Switching Characteristics, Industrial 3.3V
(continued)
Parameter
Name
Description
Min.
Typ.
Max.
Unit
All Outputs, Duty Cycle and Rise/Fall Time
t
1
OUTPUT
t
2
t
3
t
4
t
5
OE
ALL
THREE-STATE
OUTPUTS
t
6
Output Three-State Timing
[4]
CLK Outputs Jitter and Skew
t
7
CLK
OUTPUT
RELATED
CLK
t
9A
CPU Frequency Change
SELECT
CPU
OLD SELECT
NEW SELECT STABLE
F
old
F
new
t
8
& t
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2292SZI-1A0 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY2295PVI-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| CY2295PVL-196 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY2295PVL-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
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