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參數(shù)資料
| 型號： | CY2292SL-XXX |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| 中文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY2292SL-XXX |
CY2292
Document #: 38-07449 Rev. *B
Page 7 of 11
Switching Characteristics, Industrial 5.0V
Parameter
t
1
Name
Description
Min.
11.1
Typ.
Max.
13000
Unit
ns
Output Period
Clock output range, 5V
operation
CY2292I
(90 MHz)
12.5
(80 MHz)
40%
(76.923 kHz)
13000
(76.923 kHz)
60%
CY2292FI
ns
Output Duty
Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
Output clock rise time
[13]
Output clock fall time
[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
[3, 12, 14]
Frequency transition rate
50%
45%
50%
55%
t
3
t
4
t
5
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
3
5
4
15
ns
ns
ns
2.5
10
t
6
10
15
ns
t
7
< 0.25
0.5
ns
t
8
CPUCLK Slew
1.0
20.0
MHz/
ms
%
t
9A
Clock Jitter
[14]
Peak-to-peak period jitter (t
9A
max. – t
9A
min.), %
of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.) (4
MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT
<
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Lock Time for CPLL Lock Time from Power-up
Lock Time for
UPLL and SPLL
Slew Limits
CPU PLL Slew Limits
< 0.5
1
t
9B
Clock Jitter
[14]
< 0.7
1
ns
t
9C
t
9D
t
10A
t
10B
Clock Jitter
[14]
Clock Jitter
[14]
< 400
< 250
<25
<0.25
500
350
50
1
ps
ps
ms
ms
Lock Time from Power-up
CY2292I
CY2292FI
20
20
90
80
MHz
MHz
Switching Characteristics, Industrial 3.3V
Parameter
t
1
Name
Description
Min.
15
Typ.
Max.
13000
Unit
ns
Output Period
Clock output range, 3.3V
operation
CY2292I
(66.6 MHz)
16.66
(60 MHz)
40%
(76.923 kHz)
13000
(76.923 kHz)
60%
CY2292FI
ns
Output Duty
Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
Output clock rise time
[13]
Output clock fall time
[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
[3, 12, 14]
Frequency transition rate
50%
45%
50%
55%
t
3
t
4
t
5
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
3
5
4
ns
ns
ns
2.5
10
15
t
6
10
15
ns
t
7
< 0.25
0.5
ns
t
8
CPUCLK Slew
1.0
20.0
MHz/ms
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| CY2292SL-XXXT | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292FZXT | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292FT | Three-PLL General-Purpose EPROM Programmable Clock Generator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2292SL-XXXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292SXC-492 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3PLL GenPurpose EPRM Program Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2292SXC-492T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3PLL GenPurpose EPRM Program Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2292SXC-984 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3PLL GenPurpose EPRM Program Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2292SXC-984T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3PLL GenPurpose EPRM Program Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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