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參數(shù)資料
| 型號： | CY2292SC-XXX |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY2292SC-XXX |
CY2292
Document #: 38-07449 Rev. *B
Page 6 of 11
t
9A
Clock Jitter
[14]
Peak-to-peak period jitter (t
9A
max. – t
9A
min.), % of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.)
(4 MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT
<
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Lock Time from Power-up
Lock Time from Power-up
<0.5
1
%
t
9B
Clock Jitter
[14]
<0.7
1
ns
t
9C
Clock Jitter
[14]
<400
500
ps
t
9D
t
10A
t
10B
Clock Jitter
[14]
Lock Time for CPLL
Lock Time for UPLL and
SPLL
Slew Limits
<250
<25
<0.25
350
50
1
ps
ms
ms
CPU PLL Slew Limits
CY2292
CY2292F
20
20
100
90
MHz
MHz
Switching Characteristics, Commercial 3.3V
Parameter
Name
Description
Min.
12.5
Typ.
Max.
13000
Unit
ns
t
1
Output Period
Clock output range, 3.3V
operation
CY2292
(80 MHz)
15
(66.6 MHz)
40%
(76.923 kHz)
13000
(76.923 kHz)
60%
CY2292F
ns
Output Duty
Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
Output clock rise time
[13]
Output clock fall time
[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
[3, 12, 14]
Frequency transition rate
50%
45%
50%
55%
t
3
t
4
t
5
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
3
5
4
ns
ns
ns
2.5
10
15
t
6
10
15
ns
t
7
< 0.25
0.5
ns
t
8
CPUCLK Slew
1.0
20.0
MHz/
ms
%
t
9A
Clock Jitter
[14]
Peak-to-peak period jitter (t
9A
max. – t
9A
min.),
% of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.)
(4 MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT
<
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Lock Time for CPLL Lock Time from Power-up
Lock Time for
UPLL and SPLL
Slew Limits
CPU PLL Slew Limits
< 0.5
1
t
9B
Clock Jitter
[14]
< 0.7
1
ns
t
9C
t
9D
t
10A
t
10B
Clock Jitter
[14]
Clock Jitter
[14]
< 400
< 250
< 25
< 0.25
500
350
50
1
ps
ps
ms
ms
Lock Time from Power-up
CY2292
CY2292F
20
20
80
66.6
MHz
MHz
Switching Characteristics, Commercial 5.0V
(continued)
Parameter
Name
Description
Min.
Typ.
Max.
Unit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2292SC-XXXT | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292SI-XXX | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292SI-XXXT | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292FXC | FILM/M CAPACITANCE=0.015 VOLT=250 |
| CY2292FXCT | Three-PLL General-Purpose EPROM Programmable Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2292SC-XXXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Three-PLL General-Purpose EPROM Programmable Clock Generator |
| CY2292SI-1A0 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY2292SI-1T1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY2292SI-705 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY2292SI-XXX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Three-PLL General-Purpose EPROM Programmable Clock Generator |
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