參數(shù)資料
型號： CY22801FXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Universal Programmable Clock Generator (UPCG)
中文描述： 200 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝： 0.150 INCH, MS-012, SOIC-8
文件頁數(shù)： 3/7頁
文件大小： 200K
代理商： CY22801FXC
CY22801
Document #: 001-15571 Rev. **
Page 3 of 7
These jitter terms are usually given in terms of RMS,
peak-to-peak, or in the case of phase noise, dBC/Hz with
respect to the fundamental frequency. Actual jitter is
dependent on
XIN jitter and edge rate
Number of active outputs
Output frequencies
Supply voltage
Temperature
Output load
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-
μ
F ceramic
cap) of the clock and ensuring a low impedance ground to the
chip. Reducing capacitive clock output loading to a minimum
lowers current spikes on the clock edges and thus reduces
jitter.
Reducing the total number of active outputs also reduces jitter
in a linear fashion. However, it is better to use two outputs to
drive two loads than one output to drive two loads.
For additional information, refer to the application note,
Jitter
in PLL-based Systems: Causes, Effects, and Solutions
,
available at
http://www.cypress.com
.
Cypress Programmable Clocks
Cypress offers a wide range of programmable clock synthe-
sizers that can generate any other frequencies not covered by
the CY22801.
Table 1
summarizes all Cypress programmable
devices including CY22801.
Table 1. Cypress Programmable Clocks
[1]
Part #
No. of PLL
Input Freq.
Output
Freq.
1–200
1–200
0.08–200
0.08–200
3–200
3–200
27/13.5
1–200
1–200
1–200
1–200
4.2–166
Package
No. of
Outputs
up to 3
up to 3
up to 6
up to 6
up to 2
up to 6
up to 2
up to 6
up to 3
up to 6
up to 5
up to 8
Spread
Spectrum
Yes
No
No
No
Yes
Yes
No
No
No
No
No
No
VCXO
I
2
C
CY22800
CY22801
CY22050
CY22150
CY25100
CY25200
CY241V08
CY22392
CY22381
CY22393
CY22394/5
CY22388/89/91
1
1
1
1
1
1
1
3
3
3
3
4
0.5–100
1–133
1–133
1–133
8–166
3–166
27/13.5
1–166
1–166
1–166
1–166
1–100
8-SOIC
8-SOIC
16-TSSOP
16-TSSOP
8-SOIC/TSSOP
16-TSSOP
8-SOIC
16-TSSOP
8-SOIC
16-TSSOP
16-TSSOP
16/20-TSSOP,
32-QFN
Yes
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
Yes
No
No
No
No
No
Yes
No
No
Note
1. The CY22800 and CY22801 are programmed using the programming dongle included in the CY36800 InstaClock Kit. The CY3672 programmer can be used to
program all other Cypress Programmable Clocks.
[+] Feedback
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參數(shù)描述
CY22801FXCT 功能描述:鎖相環(huán) - PLL Clock Generators PCs w/100MHz CPU Bus RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY22801FXI 功能描述:鎖相環(huán) - PLL Clock Gen 200MHz RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY22801FXIT 功能描述:鎖相環(huán) - PLL Clock Gen 200MHz RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY22801KFXC 功能描述:鎖相環(huán) - PLL Prog Clk Gen 1MHz-133MHz RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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