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參數(shù)資料
| 型號： | CY2283 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs(帶ALI或VIA芯片組，AGP和3DIMM應(yīng)用于桌上型PC機(jī)的奔II，K6, 6x86 100MHz時鐘合成器/驅(qū)動器) |
| 中文描述： | PentiumII，K6，6x86 100 MHz的時鐘合成器/驅(qū)動器與阿里或威盛芯片組，AGP和3個DIMM（帶急性肺損傷或威盛芯片組，AGP接口和3DIMM應(yīng)用于桌上型電腦機(jī)的奔二，K6，6x86桌面電腦100MHz的時鐘合成器/驅(qū)動器） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 218K |
| 代理商： | CY2283 |
PRELIMINARY
Pentium/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for
Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs
Features
Mixed 2.5V and 3.3V operation
Complete clock solution for Pentium /II, Cyrix 6x86,
and AMD K6 processor-based motherboards
—Four CPU clocks at 2.5V or 3.3V
—Twelve 3.3V SDRAM clocks
[1]
—Five synchronous PCI clocks, one free-running
—One 3.3V 48 MHz USB clock
—One 3.3V Ref. clock at 14.318 MHz
—Two AGP clocks at 3.3V
Support for ALI (-1 option) and VIA (-2 option)
I
2
C Serial Configuration Interface
Full EMI control with factory-EPROM programmable
output drive and slew rate
Factory-EPROM programmable CPU clock frequencies
for custom configurations
Power-down, CPU stop, and PCI stop pins
Available in space-saving 48-pin SSOP package
Functional Description
The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,
or AMD processor-based PCs using the ALI Aladdin V (-1 op-
tion) or VIA MVP3 (-2 option) chipset.
The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There
are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI
clocks is free-running. Additionally, the part outputs twelve
3.3V SDRAM clocks
[1]
, one 3.3V USB clock at 48 MHz, and
one 3.3V reference clock at 14.318 MHz. Finally, the part out-
puts two AGP clocks running at 66.66 MHz or 60 MHz.
The CY2283 has the flexibility to work as either a one-chip or
as part of a two-chip clocking solution. In 100-MHz board de-
signs based on the ALI Aladdin V chipset, it is recommended
that the CY2283 be used with an external SDRAM buffer so-
lution such as the CY2318NZ or CY2314NZ. In this configura-
tion the SDRAM outputs on the CY2283 must be either turned
off using I
2
C or left floating. The CY231xNZ family provides the
Logic Block Diagram
XTALIN
14.318
MHz
OSC.
CPU
PLL
LOGIC
CY2283
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 12, 1998
SDRAM outputs in place of the CY2283 and can be placed in
close proximity to the SDRAM modules.
The CY2283 possesses power-down, CPU stop, and PCI stop
pins for power management control. These inputs are multi-
plexed with SDRAM clock outputs, and are selected when the
MODE pin is driven LOW. Additionally, the signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
The CY2283 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2283 Selector Guide
Clock Outputs
CPU (66.6, 75, 83.3, 100MHz)
SDRAM
PCI (30, 33.3 MHz)
USB (48MHz)
AGP (66.6, 60MHz)
Ref. (14.318 MHz)
CPU-PCI delay
AGP clock
Notes:
1.
SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the
ALI V chipset, an external CY231xNZ buffer should be used.
One free-running PCI clock
2.
-1 (ALI V)
4
12
[1]
5
[2]
1
2
1
2.5
5.5 ns
In phase
with PCI
-2 (VIA MVP3)
4
12
5
[2]
1
2
1
2.5
5.5 ns
In phase
with CPU
Pin Configuration (48 SSOP)
EPROM
XTALOUT
SDRAM [0-4],[8-11]
SDRAM6/CPU_STOP
SEL0
SEL1
SDRAM7/PCI_STOP
MODE
SCLK
SDATA
REF0 (14.318 MHz)
CPUCLK [0-3]
V
DDCPU
PCI [0-3]
PCICLK_F
STOP
STOP
LOGIC
SDRAM5/PWR_DWN
USBCLK
SYS PLL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
32
31
30
29
28
25
26
27
36
35
34
AV
DD
REF0
V
SS
XTALIN
XTALOUT
V
DDQ3
45
44
43
42
41
40
37
38
39
48
47
46
C
PCICLK_F
PCICLK0
PCICLK1
PCICLK2
PCICLK3
AGP0
V
DDQ3
V
SS
AGP1
V
SS
SDRAM11
SDRAM10
V
DDQ3
SDRAM9
SDRAM8
V
SS
SDATA
SCLK
V
DDQ3
USBCLK
SEL1
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM4
SDRAM5/PWR_DWN
V
DDQ3
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
V
SEL0
MODE
AGP
INTERFACE
CONTROL
LOGIC
SERIAL
Delay (-1 option)
/2
Delay (-2 option)
/1, /1.25, /1.5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2283PVC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs |
| CY2283PVC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs |
| CY2285 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
| CY2285PVC-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| CY2285PVC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Pentium㈢II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs |
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