參數(shù)資料
型號(hào): CY2277APAC-7M
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: 6x86, K6 Clock Synthesizer/Driver for Desktop Mobile PCs with Intel 82430TX and 2 DIMMs or 3 SO-DIMMs
中文描述: 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 6 X 12 MM, TSSOP2-48
文件頁數(shù): 13/19頁
文件大小: 206K
代理商: CY2277APAC-7M
CY2277A
Document #: 38-07332 Rev. *A
Page 13 of 19
Timing Requirement for the SMBus
Parameter
t
10
t
11
t
12
t
13
t
14
t
15
t
16
Description
Min.
0
4.7
4
4.7
4
4.7
Max.
100
Unit
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
SCLK Clock Frequency
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated.
The LOW period of the clock.
The HIGH period of the clock.
Setup time for start condition. (Only relevant for a repeated start condition.)
Hold time DATA
for CBUS compatible masters.
for SMBus devices
DATA input set-up time
Rise time of both SDATA and SCLK inputs
Fall time of both SDATA and SCLK inputs
Set-up time for stop condition
5
0
t
17
t
18
t
19
t
20
Switching Waveforms
250
ns
μ
s
ns
μ
s
1
300
4.0
Duty Cycle Timing
t
1A
t
1B
CPUCLK Outputs HIGH/LOW Time
OUTPUT
V
DD
0V
t
1C
t
1D
All Outputs Rise/Fall Time
OUTPUT
t
2
t
3
V
DD
0V
t
2
t
4
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