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參數(shù)資料
| 型號： | CY2277APAC-7M |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 6x86, K6 Clock Synthesizer/Driver for Desktop Mobile PCs with Intel 82430TX and 2 DIMMs or 3 SO-DIMMs |
| 中文描述： | 66.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6 X 12 MM, TSSOP2-48 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 206K |
| 代理商： | CY2277APAC-7M |
CY2277A
Document #: 38-07332 Rev. *A
Page 10 of 19
Switching Characteristics (-1M, -7M, -12M)
[9, 10, 11]
Parameter
t
1
Output
CPUCLK
SDRAM
USBCLK
REF [0,1]
IOAPIC
PCI
CPUCLK,
IOAPIC
Description
Test Conditions
Min.
45
Typ.
50
Max.
55
Unit
%
Output Duty Cycle
[12]
t
1
= t
1A
÷
t
1B
t
1
t
2
Output Duty Cycle
[12]
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
PCI Clock Rising and
Falling Edge Rate
USB, REF0 Clock Rising
and Falling Edge Rate
SDRAM Rising and Fall-
ing Edge Rate
REF1 Rising and Falling
Edge Rate
CPU Clock Rise Time
USB Clock Rise Time
CPU Clock Fall Time
USB Clock Fall Time
CPU-CPU Clock Skew
PCI-PCI Clock Skew
SDRAM-SDRAM Clock
Skew
CPU-PCI Clock Skew
-1M, -12M
CPU-PCI Clock Skew
-7M
CPU-SDRAM Clock
Skew
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
t
1
= t
1A
÷
t
1B
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
CPU clocks at 66.66 MHz
45
0.60
50
55
4.0
%
V/ns
t
2
PCI
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
0.65
4.0
V/ns
t
2
USBCLK,
REF0
SDRAM
Between 0.4V and 2.4V
0.65
4.0
V/ns
t
2
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
Between 0.4V and 2.4V
0.70
4.0
V/ns
t
2
REF1
0.5
2.0
V/ns
t
3
t
3
t
4
t
4
t
5
t
5
t
5
CPUCLK
USBCLK
CPUCLK
USBCLK
CPUCLK
PCICLK
SDRAM
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.0V
Between 2.0V and 0.4V, V
DDCPU
= 2.5V
Between 2.0V and 0.4V
Measured at 1.25V, V
DDCPU
= 2.5V
Measured at 1.5V
Measured at 1.5V
0.4
2.4
2.5
2.4
2.5
250
400
300
ns
ns
ns
ns
ps
ps
ps
0.4
100
t
6
CPUCLK,
PCICLK
CPUCLK,
PCICLK
CPUCLK,
SDRAM
CPUCLK
SDRAM
PCICLK
USBCLK,
IOCLK
CPUCLK,
PCICLK,
SDRAM
CPU, PCI,
SDRAM
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, V
DDCPU
= 2.5V
Measured at 1.25V for 2.5V clocks
Measured at 1.5V
Measured at 1.5V
Measured at 1.5V
1.0
2.0
6.0
ns
t
6
750
ps
t
7
600
ps
t
8
t
8
t
8
t
8
525
600
400
900
ps
ps
ps
ps
t
9
Power-up Time
CPU, PCI, and SDRAM clock stabiliza-
tion from power-up
3
ms
t
10
Frequency Slew Rate
Rate of change of frequency
2
MHz/
ms
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