參數(shù)資料
型號(hào)： CY22394ZI-XXXT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： XO, clock
英文描述： -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash
中文描述： 375 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝： 4.40 MM, MO-153, TSSOP-16
文件頁(yè)數(shù)： 10/19頁(yè)
文件大?。?/td> 235K
代理商： CY22394ZI-XXXT
CY22393
CY22394
CY22395
Document #: 38-07186 Rev. *B
Page 10 of 19
Serial Programming Interface Timing
SDAT Write
Multiple
Contiguous
Registers
Start Signal
Device
Address
7-bit
R/W = 0
1 Bit
8-bit
Register
Address
(XXH)
Slave
ACK
1 Bit
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH)
Stop Signal
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH+1)
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH+2)
Slave
ACK
1 Bit
8-bit
Register
Data
(FFH)
Slave
ACK
1 Bit
8-bit
Register
Data
(00H)
Slave
ACK
1 Bit
Slave
ACK
1 Bit
SDAT Read
Start Signal
Device
Address
7-bit
R/W = 1
1 Bit
8-bit
Register
Data
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Stop Signal
SDAT Read
Multiple
Contiguous
Registers
Start Signal
Device
Address
7-bit
R/W = 0
1 Bit
8-bit
Register
Address
(XXH)
Slave
ACK
1 Bit
Slave
ACK
1 Bit
7-bit
Device
Address
+R/W=1
Stop Signal
Master
ACK
1 Bit
8-bit
Register
Data
(XXH)
Master
ACK
1 Bit
Master
ACK
1 Bit
8-bit
Register
Data
(XXH+1)
Master
ACK
1 Bit
8-bit
Register
Data
(FFH)
Master
ACK
1 Bit
8-bit
Register
Data
(00H)
Master
ACK
1 Bit
Master
ACK
1 Bit
Current
Address
Read
Repeated
Start bit
Figure 2. Data Frame Architecture
SDAT
SCLK
Data Valid
Transition
to next Bit
CLK
LOW
CLK
HIGH
VIH
VIL
t
SU
t
DH
Figure 3. Data Valid and Data Transition Periods
SDAT
SCLK
START
Transition
to next Bit
STOP
Figure 4. Start and Stop Frame
相關(guān)PDF資料
PDF描述
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