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參數(shù)資料
| 型號： | CY2039 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 208K |
| 代理商： | CY2039 |
CY2037
3
On the other hand, the CY2037-3 contains a frequency select
function in place of the power down and output enable modes.
For example, consumer products often require frequency com-
patibility with different electrical standards around the world.
With this frequency select feature a product that incorporates
the CY2037-3 could be compatible with both NTSC for North
American and PAL for Europe simply by changing the FS line.
The twice programmable feature is also lost in the CY2037-3,
because the second EPROM row is now being used for the
alternate frequency.
EPROM Configuration Block
Table 1
summarizes the features which are configurable by
EPROM.
Please
refer
to
Programming Specification” for further details. The specifiction
can be obtained from your Cypress factory representative.
the
“7C8038x/7C8034X
PLL Output Frequency
The CY2037 contains a high resolution PLL with 12 bit multi-
plier and 10 bit divider.The output frequency of the PLL is de-
termined by the following formula:
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
Power Management features (except CY2037-3)
The CY2037 contains EPROM programmable PWR_DWN
and OE functions. If Powerdown is selected, all active circuitry
on the chip is shut down when the control pin goes low. The
oscillator and PLL circuits must re-lock when the part leaves
Powerdown Mode. If Output Enable mode is selected, the out-
put is tri-stated and weakly pulled low when the Control pin
Die Pad Summary
goes low. In this mode the oscillator and PLL circuits continue
to operate, allowing a rapid return to normal operation when
the Control input is deasserted.
In addition, the PWR_DWN and OE modes can be pro-
grammed to occur synchronously or asynchronously with re-
spect to the output signal. When the asynchronous setting is
used, the powerdown or output disable occurs immediately (al-
lowing for logic delays) irrespective of position in the clock cy-
cle. However, when the synchronous setting is used, the part
waits for a falling edge at the output before powerdown or out-
put enable signalis initiated, thus preventing output glitches. In
either asynchronous or synchronous setting, the output is al-
ways enabled synchronously by waiting for the next falling
edge of the output.
Crystal Oscillator Tuning Circuit
The CY2037 contains a unique tuning circuit to fine-tune the
output frequency of the device. The tuning circuit consists of
an array of eleven load capacitors on both sides of the oscilla-
tor drive inverter. The capacitor load values are EPROM pro-
grammable and can be increased in small increments. As the
capacitor load is increased the circuit is fine-tuned to a lower
frequency. The capacitor load values vary from 0.17 pF to 8 pF
for a 100:1 total control ratio. The tuning increments are shown
in the table below. Please refer to the “7C8038x/7C8034x Pro-
grammimg Specification” for futher details.
Difference Between CY2037A and CY2037-2
The CY2037A contains a shadow register in addition to the
EPROM register. The shadow register is an exact copy of the
EPROM register and is the default register when the Valid bit
is not set. It is useful when the prototype or production envi-
ronment calls for measuring and adjusting the CLKOUT fre-
quency numerous times. Multiple adjustments can be per-
formed with the shadow register. Once the desired frequency
is achieved the EPROM register is permanently programmed.
Some production flows do not require the use of the shadow
register. If this is the case, then the CY2037-2 is the device of
choice. The CY2037-2 has a disabled shadow register.
The CY2037-3 contains the shadow register.
Frequency Select Feature of CY2037-3
The CY2037-3 contains a frequency select function in place of
the powerdown and the output enable functions. With the
frequency select feature, customers can switch two different
frequencies that are configured in the two EPROM rows The-
definition of the Frequency select pin (FS) is shown in the table
below.
Table 1. EPROM Adjustable Features
Adjust
Frequency
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Oscillator Tuning (load capacitance values)
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing
(synchronous or asynchronous)
F
PLL
2
P
+
5
)
+
2
(
)
(
Q
F
REF
=
Name
V
DD
V
SS
X
D
X
X
Die Pad
1,2
8,9
4
3
Description
Voltage supply
Ground
Crystal connection.
No Connect. ( For customers not bonding X
D
or X
G
pad to external pins, an alternative bonding
option would be shorting this pad to XD pad.)
Crystal connection.
CY2037A and CY2037-2 - EPROM programmable power down or output enable pad.
CY2037-3 - Frequency Select.
Serves as V
PP
in programming mode for all devices
Clock output. Also serves as three-state input during programming.
No Connect. (Do not bond to these pads)
X
G
PD/OE or FS
6
7
CLKOUT
N/C
11
5,10
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PDF描述 |
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| CY2040WAF | Clocks and Buffers |
| CY2077SC-XXX | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| CY2077SI-XXX | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| CY2077ZC-XXX | MISCELLANEOUS CLOCK GENERATOR|TSSOP|8PIN|PLASTIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2040 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input |
| CY2040-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input |
| CY2040-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input |
| CY2040WAF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY2040ZC-3 | 制造商:Cypress Semiconductor 功能描述: |
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