參數(shù)資料
型號(hào): CXD3511AQ
廠商: Sony Corporation
英文描述: Digital Signal Driver/Timing Generator
中文描述: 數(shù)字信號(hào)驅(qū)動(dòng)器/時(shí)序發(fā)生器
文件頁(yè)數(shù): 11/84頁(yè)
文件大小: 569K
代理商: CXD3511AQ
11
CXD3511AQ
Electrical Characteristics
DC Characteristics
(Topr =
20 to +75
°
C, V
SS
= 0V)
1
Input pins other than those indicated in items Input voltage 2 and Input voltage 3.
2
V
IH3
> VC (max.) and V
IL3
< VC (min.).
3
Tj [
°
C]
Toprmax [
°
C] +
θ
ja [
°
C/W]
×
P
D
[W].
(Tj = 125 [
°
C], Toprmax = 75 [
°
C],
θ
ja = 16 [
°
C/W], when mounted on a 4-layer substrate)
AC Characteristics
(Topr =
20 to +75
°
C, V
DD1
= 2.5 ± 0.2V, V
DD2
= 3.3 ± 0.3V, V
SS
= 0V)
4
Output pins other than CLKOUT, PO1 to PO5, RGT, XRGT and DWN.
Clock input period
Input setup time
Input hold time
Output rise/fall
delay time
Output rise/fall
delay time
Cross-point time
difference
HCK1 duty
HCK2 duty
Phase compensation
PLL operating
frequency
t
is
t
ih
t
or/
t
of
t
or/
t
of
t
t
h/(
t
h +
t
l)
t
l/(
t
h +
t
l)
CLKP CLKN, CLKC
RGB input, OSD input,
HDIN, VDIN
4
CLKOUT
HCK1, HCK2, DCK1,
DCK1X, DCK2, DCK2X
HCK1
HCK2
CL = 20pF
CL = 50pF
CL = 20pF
CL = 20pF
CL = 20pF
PLLDIV = L
PLLDIV = H
5
2.5
1.5
2.0
2.5
5.0
48
48
55
27.5
4.0
4.5
50
50
8.0
8.5
5.0
52
52
100
55
ns
%
MHz
Item
Symbol
Applicable pins
Conditions
Min.
Typ.
Max.
Unit
Supply
voltage
Input
voltage 1
Input
voltage 2
Input
voltage 3
Output
voltage
Current
consumption
V
DD1
V
DD2
V
IH1
V
IL1
V
IH2
V
IL2
VC
2
V
IH3
V
IL3
V
OH
V
OL
P
D
3
1
HDIN, VDIN, PCTL,
PCLK, PDAT0 to PDAT9
CLKP CLKN
All output pins
CMOS input cell
CMOS Schmitt
trigger input cell
Small-amplitude
differential input
CLKP = 200MHz
2.3
3.0
2.0
0.3
0.8V
DD2
0.3
1.718
1.868
V
SS
V
DD2
0.5
V
SS
2.5
3.3
2.0
VC + 0.4
VC
0.4
2600
2.7
3.6
V
DD2
+ 0.3
0.8
V
DD2
+ 0.3
0.2V
DD2
2.281
V
DD2
2.131
V
DD2
0.2
3120
Item
Symbol
Applicable pins
Conditions
Min.
Typ.
Max.
V
mW
Unit
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