參數(shù)資料
型號: CXD3412
廠商: Sony Corporation
英文描述: Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
中文描述: 時序發(fā)生器和幀讀出CCD圖像傳感器信號處理器
文件頁數(shù): 30/46頁
文件大?。?/td> 383K
代理商: CXD3412
C
Chart-3
Vertical Direction Timing Chart
MODE
AF1 mode
Applicable CCD image sensor
ICX412
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern, it is 171H + 1296ck units.
High-speed sweep block starts from 159H.
VD
SUB
CLPOB
CLPDM
V1A
Frame shift block
V1B
V2
V3A
V3B
V4
CCD OUT
PBLK
ID/EXP
WEN
HD
6
4
6
4
D
E
E
E
D
E
144
144
Wide CLPOB
High-speed
sweep block
Frame shift block
High-speed
sweep block
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
131
2
14
131
2
14
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