參數(shù)資料
型號: CXD3059AR
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost
中文描述: CD數(shù)字信號處理器具有內(nèi)置的RF放大器和數(shù)字伺服數(shù)字高
文件頁數(shù): 6/27頁
文件大?。?/td> 337K
代理商: CXD3059AR
– 6 –
CXD3059AR
Pin
No.
Symbol
I/O
Description
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
IOV
DD
2
DOUT
TEST
TES1
IOVss2
NC
XV
SS
XTAO
XTAI
XV
DD
AV
DD
1
AOUT1
VREFL
AV
SS
1
AV
SS
2
VREFR
AOUT2
AV
DD
2
NC
IOV
DD
0
RMUT
LMUT
NC
XTSL
IOV
SS
0
XTACN
SQSO
SQCK
SBSO
EXCK
XRST
SYSM
D ATA
V
SS
XLAT
O
I
I
O
I
O
O
O
O
O
O
I
I
O
I
O
I
I
I
I
I
I/O digital power supply.
Digital Out output.
Test pin. Normally GND.
Test pin. Normally GND.
I/O digital GND.
Master clock GND.
Crystal oscillation circuit output.
Crystal oscillation circuit input.
Master clock power supply.
Analog power supply.
Lch analog output.
Lch reference voltage.
Analog GND.
Analog GND.
Rch reference voltage.
Rch analog output.
Analog power supply.
I/O digital power supply.
Rch "0" detection flag.
Lch "0" detection flag.
Crystal selection input.
Low when the crystal is 16.9344MHz;
high when the crystal is 33.8688MHz.
I/O digital GND.
Oscillation circuit control.
Self-oscillation when high, oscillation stop when low.
Subcode Q 80-bit and PCM peak and level data output.
CD TEXT data output.
SQSO readout clock input.
Subcode P to W serial output.
SBSO readout clock input.
System reset. Reset when low.
Mute input. Muted when high.
Serial data input from CPU.
Internal digital GND.
Latch input from CPU. The serial data is latched at the falling edge.
Power
supply
1, 0
1, 0
1, 0
1, 0
1, 0
X'tal
2.5V
Digital
I/O = 3.3V
Internal =
2.5V
Lch
3.3V
Rch
3.3V
Digital
I/O = 3.3V
Internal =
2.5V
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