參數(shù)資料
型號(hào): CXD3017Q
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC(CD數(shù)字信號(hào)處理器(內(nèi)置數(shù)字伺服系統(tǒng)和 D/A轉(zhuǎn)換器))
中文描述: CD數(shù)字信號(hào)處理器,具有內(nèi)置數(shù)字伺服和DAC(光盤數(shù)字信號(hào)處理器(內(nèi)置數(shù)字伺服系統(tǒng)和的D / A轉(zhuǎn)換器))
文件頁數(shù): 6/117頁
文件大?。?/td> 778K
代理商: CXD3017Q
6
CXD3017Q
Pin
No.
Symbol
I/O
Output
values
Description
Analog power supply.
L ch analog output.
L ch operational amplifier input.
L ch LINE output.
Analog GND.
Analog GND.
R ch LINE output.
R ch operational amplifier output.
R ch analog output.
Analog power supply.
R ch zero detection flag.
L ch zero detection flag.
1, 0
1, 0
O
I
O
O
I
O
O
O
AV
DD
1
AOUT1
AIN1
LOUT1
AV
SS
1
AV
SS
2
LOUT2
AIN2
AOUT2
AV
DD
2
RMUT
LMUT
69
70
71
72
73
74
75
76
77
78
79
80
Notes)
PCMD is a MSB first, two's complement output.
GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
The GFS signal goes high when the frame sync and the insertion timing match.
RFCK is derived from the crystal accuracy, and has a cycle of 136μs.
C2PO represents the data error status.
XROF is generated when the 16K RAM exceeds the ±4F jitter margin.
Monitor Pin Output Combinations
Command bit
Output data
MTSL1
0
0
1
0
1
0
XUGF
MNT1
RFCK
XPCK
MNT0
XPCK
GFS
MNT3
XROF
C2PO
C2PO
GTOP
MTSL0
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