參數(shù)資料
型號(hào)： CXD3011R-1
廠商： Sony Corporation
英文描述： Hook-Up Wire; Conductor Size AWG:26; No. Strands x Strand Size:7 x 34; Jacket Color:White/Yellow; Cable/Wire MIL SPEC:MIL-W-16878/1 Type B; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
中文描述： CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁(yè)數(shù)： 104/160頁(yè)
文件大?。?/td> 1512K
代理商： CXD3011R-1
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CXD3011R-1
DAC block mute operation
Soft mute
Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.
When attenuation data of 000 (Hex) is set
When the $9X commands DAC SMUTL and DAC SMUTR are set to 1
Forced mute
Forced mute results when the $AX command FMUT is set to 1.
Forced mute fixes the PWM output. (Low for left channel, high for right channel)
Zero detection mute
Setting $9X command ZMUT to 1 enables forced mute, when zero data is detected for both the left and
right channels. (See "Zero data detection".)
LRCK Synchronization
Synchronization is performed at the first rising edge of the LRCK input when reset.
After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must
be performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.
When the XTSL pin switches between high and low
When the $9X command DSPB setting changes
When the $9X command MCSL setting changes
When operation switches between CLV mode and CAV mode
LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in these cases as well.
For resynchronization, set the $9X command XWOC to 0 or the external pin XWO to low, wait for one
LRCK cycle or more, and then set XWOC to 1 and XWO to high.
When setting XWOC to 0 or the external pin XWO to low, be sure to set the $9X command SYCOF to 0
beforehand.
Soft mute on
Soft mute off
Soft mute off
23.2 [ms]
23.2 [ms]
0dB
–
∞
dB
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