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參數(shù)資料
| 型號(hào)： | CXD3008Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo |
| 中文描述： | CD數(shù)字信號(hào)處理器的內(nèi)置數(shù)碼舵機(jī) |
| 文件頁數(shù)： | 11/131頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | CXD3008Q |
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CXD3008Q
Contents
[1] CPU Interface
§ 1-1. CPU Interface Timing .................................................................................................................... 12
§ 1-2. CPU Interface Command Table .................................................................................................... 12
§ 1-3. CPU Command Presets ................................................................................................................ 23
§ 1-4. Description of SENS Signals......................................................................................................... 30
[2] Subcode Interface
§ 2-1. P to W Subcode Readout.............................................................................................................. 56
§ 2-2. 80-bit Sub-Q Readout.................................................................................................................... 56
[3] Description of Modes
§ 3-1. CLV-N Mode.................................................................................................................................. 63
§ 3-2. CLV-W Mode................................................................................................................................. 63
§ 3-3. CAV-W Mode................................................................................................................................. 63
§ 3-4. VCO-C mode................................................................................................................................. 64
[4] Description of Other Functions
§ 4-1. Channel Clock Regeneration by Digital PLL Circuit ...................................................................... 67
§ 4-2. Frame Sync Protection.................................................................................................................. 69
§ 4-3. Error Correction............................................................................................................................. 69
§ 4-4. DA Interface................................................................................................................................... 70
§ 4-5. Digital Out...................................................................................................................................... 72
§ 4-6. Servo Auto Sequence.................................................................................................................... 73
§ 4-7. Digital CLV..................................................................................................................................... 81
§ 4-8. Playback Speed............................................................................................................................. 82
§ 4-9. Asymmetry Correction................................................................................................................... 83
§ 4-10. CD TEXT Data Demodulation ....................................................................................................... 84
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System.............................................................. 86
§ 5-2. Digital Servo Block Master Clock (MCK)....................................................................................... 87
§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ....................................................... 88
§ 5-4. E: F Balance Adjustment Function ................................................................................................ 89
§ 5-5. FCS Bias Adjustment Function...................................................................................................... 89
§ 5-6. AGCNTL Function ......................................................................................................................... 91
§ 5-7. FCS Servo and FCS Search ......................................................................................................... 93
§ 5-8. TRK and SLD Servo Control ......................................................................................................... 94
§ 5-9. MIRR and DFCT Signal Generation.............................................................................................. 95
§ 5-10. DFCT Countermeasure Circuit...................................................................................................... 96
§ 5-11. Anti-Shock Circuit.......................................................................................................................... 96
§ 5-12. Brake Circuit.................................................................................................................................. 97
§ 5-13. COUT Signal ................................................................................................................................. 98
§ 5-14. Serial Readout Circuit.................................................................................................................... 98
§ 5-15. Writing to Coefficient RAM ............................................................................................................ 99
§ 5-16. PWM Output.................................................................................................................................. 99
§ 5-17. Servo Status Changes Produced by LOCK Signal........................................................................ 100
§ 5-18. Description of Commands and Data Sets ..................................................................................... 100
§ 5-19. List of Servo Filter Coefficients...................................................................................................... 121
§ 5-20. Filter Composition.......................................................................................................................... 123
§ 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 129
[6] Application Circuit
.................................................................................................................................. 130
Explanation of abbreviations AVRG:
Average
Auto gain control
Focus
Tracking
Sled
Defect
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD3009Q | CD Digital Signal Processor(CD數(shù)字信號(hào)處理器) |
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| CXD3017Q | CD Digital Signal Processor with Built-in Digital Servo and DAC(CD數(shù)字信號(hào)處理器（內(nèi)置數(shù)字伺服系統(tǒng)和 D/A轉(zhuǎn)換器）) |
| CXD3027R | CD Digital Signal Processor with Built-in Digital Servo +Shock-Proof Memory Controller + Digital High & Bass Boost(CD數(shù)字信號(hào)處理器(內(nèi)置數(shù)字伺服系統(tǒng)、防震存儲(chǔ)器控制器、數(shù)字式高&低音提升電路）) |
| cxd3027 | CD Audio Digital Signal-Processing LSI Device with On-Chip Digital Servo System Allows Listening without Sound Skipping |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3009Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor |
| CXD3011R-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD3017Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD3018Q/R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD Digital Signal Processor with Built-in DigitalServo and DAC |
| CXD3021 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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