參數(shù)資料
型號(hào)： CXD3005R
廠商： Sony Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述： CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁(yè)數(shù)： 15/136頁(yè)
文件大?。?/td> 1682K
代理商： CXD3005R
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
– 15 –
CXD3005R
Contents
[1] CPU Interface
§1-1.
§1-2.
§1-3.
§1-4.
CPU Interface Timing ........................................................................................................................ 16
CPU Interface Command Table ........................................................................................................ 16
CPU Command Presets .................................................................................................................... 26
Description of SENS Signals ............................................................................................................. 31
[2] Subcode Interface
§2-1.
P to W Subcode Readout .................................................................................................................. 65
§2-2.
80-bit Sub Q Readout ........................................................................................................................ 65
[3] Description of Modes
§3-1.
CLV-N Mode ...................................................................................................................................... 71
§3-2.
CLV-W Mode ..................................................................................................................................... 71
§3-3.
CAV-W Mode ..................................................................................................................................... 71
[4] Description of Other Functions
§4-1.
Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 73
§4-2.
Frame Sync Protection ...................................................................................................................... 75
§4-3.
Error Correction ................................................................................................................................. 75
§4-4.
DA Interface ....................................................................................................................................... 76
§4-5.
Digital Out .......................................................................................................................................... 79
§4-6.
Servo Auto Sequence ....................................................................................................................... 80
§4-7.
Digital CLV ......................................................................................................................................... 88
§4-8.
Playback Speed ................................................................................................................................ 89
§4-9.
DAC Block Playback Speed .............................................................................................................. 90
§4-10. DAC Block Input Timing .................................................................................................................... 90
§4-11. Asymmetry Compensation ................................................................................................................ 91
§4-12. CXD3005 Clock System .................................................................................................................... 92
[5] Description of Servo Signal Processing System Functions and Commands
§5-1.
General Description of the Servo Signal Processing System ............................................................ 93
§5-2.
Digital Servo Block Master Clock (MCK) ........................................................................................... 94
§5-3.
AVRG Measurement and Compensation .......................................................................................... 94
§5-4.
E:F Balance Adjustment Function ..................................................................................................... 96
§5-5.
FCS Bias Adjustment Function .......................................................................................................... 96
§5-6.
AGCNTL Function ............................................................................................................................. 98
§5-7.
FCS Servo and FCS Search ........................................................................................................... 100
§5-8.
TRK and SLD Servo Control ........................................................................................................... 101
§5-9.
MIRR and DFCT Signal Generation ................................................................................................ 102
§5-10. DFCT Countermeasure Circuit ........................................................................................................ 103
§5-11. Anti-Shock Circuit ............................................................................................................................ 103
§5-12. Brake Circuit .................................................................................................................................... 104
§5-13. COUT Signal ................................................................................................................................... 105
§5-14. Serial Readout Circuit ...................................................................................................................... 105
§5-15. Writing to the Coefficient RAM ........................................................................................................ 106
§5-16. PWM Output .................................................................................................................................... 106
§5-17. DIRC Input Pin ................................................................................................................................. 108
§5-18. Servo Status Changes Produced by the LOCK Signal ................................................................... 109
§5-19. Description of Commands and Data Sets ....................................................................................... 109
§5-20. List of Servo Filter Coefficients ........................................................................................................ 124
§5-21. Filter Composition ............................................................................................................................ 126
§5-22. TRACKING and FOCUS Frequency Response .............................................................................. 133
[6] Application Circuit
.................................................................................................................................. 134
Explanation of abbreviations
AVRG:
AGCNTL: Auto gain control
FCS:
Focus
TRK:
Tracking
SLD:
Sled
DFCT:
Defect
Average
相關(guān)PDF資料
PDF描述
CXD3008Q CD Digital Signal Processor with Built-in Digital Servo
CXD3009Q CD Digital Signal Processor(CD數(shù)字信號(hào)處理器)
CXD3011R-1 Hook-Up Wire; Conductor Size AWG:26; No. Strands x Strand Size:7 x 34; Jacket Color:White/Yellow; Cable/Wire MIL SPEC:MIL-W-16878/1 Type B; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
CXD3017Q CD Digital Signal Processor with Built-in Digital Servo and DAC(CD數(shù)字信號(hào)處理器（內(nèi)置數(shù)字伺服系統(tǒng)和 D/A轉(zhuǎn)換器）)
CXD3027R CD Digital Signal Processor with Built-in Digital Servo +Shock-Proof Memory Controller + Digital High & Bass Boost(CD數(shù)字信號(hào)處理器(內(nèi)置數(shù)字伺服系統(tǒng)、防震存儲(chǔ)器控制器、數(shù)字式高&低音提升電路）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD3008Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo
CXD3009Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor
CXD3011R-1 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC
CXD3017Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC
CXD3018Q/R 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD Digital Signal Processor with Built-in DigitalServo and DAC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*