參數(shù)資料
型號： CXD2598Q
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC(數(shù)字式CD信號處理器（內(nèi)置數(shù)字式伺服系統(tǒng)和D/A轉(zhuǎn)換器）)
中文描述： CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服和DAC（數(shù)字式光盤信號處理器（內(nèi)置數(shù)字式伺服系統(tǒng)和的D / A轉(zhuǎn)換器））
文件頁數(shù)： 92/147頁
文件大?。?/td> 1113K
代理商： CXD2598Q
§4-10. DAC Block Input Timing
The DAC block input timing is shown in Timing Chart 4-12.
The CXD2598Q enables data transfer from the CD signal processor block to the DAC block via an external
route. This makes it possible to send data to the DAC block via an external audio DSP, etc.
When the data is input to the DAC block without using an audio DSP, either EMPH, LRCK, BCK and PCMD
must be connected directly with EMPHI, LRCKI, BCKI and PCMDI outside the LSI, or the OUTL0 command of
$8X must be set to 1. Note that when the OUTL0 command of $8X is set to 1, the EMPH, LRCK, BCK and
PCMD outputs are low.
§4-11. Description of DAC Block Functions
Zero data detection
When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is performed
independently for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected with the ZDPL command of $9X.
When zero data is detected
When a high signal is input to the SYSM pin
When the DAC SMUTL and DAC SMUTR commands of $9X are set (The flags change independently
for the left and right channels.)
The mute flag outputs during initialize are as follows. (When zero data is input from LRCKI, BCKI and
PCMDI, and ZDPL of address $9 and MCSL of address $A are the initial values for the period in the figure
below.)
– 92 –
CXD2598Q
A
Y1
B
Y3
C
Y2
23.2 [ms]
–
∞
000 (H)
0dB
400 (H)
XRST
LMUT
RMUT
Approximately 370ms when crystal = 16.9344MHz
Approximately 185ms when crystal = 33.8688MHz
Attenuation operation
Assuming the attenuation commands X1, X3 and X2, the corresponding audio outputs are Y1, Y2 and Y3
(Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the
command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and
approaches Y2. In addition, when the command X3 is sent before the audio output reaches Y2 (B or C in the
figure), the audio output approaches Y3 from the value (B or C in the figure) at that point.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD2719Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder
CXD2720Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Digital Signal Processor for Karaoke
CXD2720Q-2 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder
CXD2721Q-1 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Digital Signal Processor for Karaoke
CXD2724AQ-1 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder
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