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—10—
CXD1196AR
2. SRAM interface
(1) Read
(2) Write
Item
Address setting time (with respect to XMOE
↓
)
Address holding time (with respect to XMOE
↑
)
Data setting time (with respect to XMOE
↑
)
Data holding time (with respect to XMOE
↑
)
L level XMOE pulse width
Symbol
Tsao
Thao
Tsdo
Thdo
Toel
Min.
T
1
–30
T
1
–10
50 (100)
10 (20)
Typ.
2 T
1
Max.
Unit
ns
ns
ns
ns
ns
MA14-MA0
XMWR
MDB7-MDB0
Tsamw
Tmwl
Thamw
Tdmw
Tfmw
Item
Address setting time (with respect to XMWR
↓
)
Address holding time (with respect to XMWR
↑
)
Data delay time (with respect to XMWR
↓
)
Data float time (with respect to XMWR
↑
)
L level XMWR pulse width
Symbol
Tsamw
Thamw
Tdmw
Tfmw
Tmwl
Min.
T
1
–30
T
1
–10
10
Typ.
2 T
1
Max.
0
Unit
ns
ns
ns
ns
ns
T
1
=
59 ns :
238 ns : XSLOW = ‘L’
XSLOW = ‘H’
Note that XSLOW is bit 7 of DRVIF register.
When XSLOW = ‘H’ , make sure that the CXD1196AR is connected to an SRAM with an access time of
less than 120 ns.
When XSLOW = ‘L’ , make sure that the CXD1196AR is connected to an SRAM with an access time of less
than 320 ns.
{
MA14-MA0
XMOE
MDB7-MDB0
Tsao
Toel
Thao
Tsdo
Thdo