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參數(shù)資料
| 型號(hào)： | CV141PAG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 141 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | GREEN, TSSOP-48 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 81K |
| 代理商： | CV141PAG8 |
COMMERCIALTEMPERATURERANGE
8
IDTCV141
1-TO-8DIFFERENTIALCLOCKBUFFER
SRC_STOP = DRIVEN, PWRDWN = DRIVEN
DIF (Free Running)
SRC_Stop
PWRDWN
(1)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP = TRISTATE, PWRDWN = DRIVEN
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_Stop
PWRDWN
(1)
SRC STOP FUNCTIONALITY
The SRC_STOP signal is an input controlling DIF[7:0] and DIF[7:0] # outputs. This signal can be asserted asynchronously. SRC_STOP is active high
when OE_INV = HIGH (see OE_INV table).
NOTE:
1.
The polarity depends on OE_INV.
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