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參數(shù)資料
| 型號(hào)： | CV141PAG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 141 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | GREEN, TSSOP-48 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | CV141PAG8 |
COMMERCIALTEMPERATURERANGE
2
IDTCV141
1-TO-8DIFFERENTIALCLOCKBUFFER
PIN CONFIGURATION
Symbol
Description
Min
Max
Unit
VDDA
3.3V Core Supply Voltage
4.6
V
VDDIN
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
TSTG
Storage Temperature
–65
+150
° C
TAMBIENT
Ambient Operating Temperature
0
+70
° C
TCASE
Case Temperature
+115
° C
ESD Prot
Input ESD Protection
2000
V
Human Body Model
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SSOP/ TSSOP
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
LOCK
VDDA
VSSA
IREF
OE_7
OE_4
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
VSS
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP
PWRDWN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SRC_DIV2#
VDD
VSS
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
VSS
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2#
VSS
VDD
DIF_3
DIF_3#
PLL/BPASS#
DIF_2
SCL
SDA
VSS
(1)
OE FUNCTIONALITY [OE_INV = 0]
OE_[7:0] - Pin OE_[7:0] - SMBus bit
DIF_[7:0]
DIFF_[7:0]#
1
Normal
1
0
Tristate
0
1
Tristate
0
Tristate
HIGH_BW# SELECTION
HIGH_BW# = 0
HIGH_BW#=1
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
PLL BW
2
3
4
0.7
1
1.4
MHz
PLL Peaking
—
13
—
13
dB
OE_INV
OE_INV = 0
OE_INV = 1
OE_[7:0]
Active HIGH
Active LOW
PWRDWN
Active LOW
Active HIGH
SRC_STOP
Active LOW
Active HIGH
OE FUNCTIONALITY [OE_INV = 1]
OE_[7:0] - Pin OE_[7:0] - SMBus bit
DIF_[7:0]
DIFF_[7:0]#
1
Tristate
1
0
Tristate
0
1
Normal
0
Tristate
NOTE:
1. See OE_INV table for active HIGH or active LOW.
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