參數(shù)資料
型號: CS8413
廠商: Electronic Theatre Controls, Inc.
英文描述: 96 KHZ DIGITAL AUDIO RECEIVER
中文描述: 96 kHz的數(shù)字音頻接收器
文件頁數(shù): 5/38頁
文件大?。?/td> 646K
代理商: CS8413
CS8413 CS8414
DS240F1
13
and output random data if ROER is not set. The
conditions that activate ERF are those reported in
SR2 and enabled in IER2. Figure 10 illustrates the
modes selectable by SDF2-SDF0 and FSF1-FSF0.
MSTR, which in most applications will be set to
one, determines whether FSYNC and SCK are out-
puts (MSTR = 1) or inputs (MSTR = 0). When
FSYNC and SCK are inputs (slave mode) the audio
data can be read twice or missed if the device con-
trolling FSYNC and SCK is on a different time-
base than the CS8413. If the audio data is read
twice or missed, the SLIP bit in SR1 is set. SCED
selects the SCK edge to output data on. SCED high
causes data to be output on the falling edge, and
SCED low causes data to be output on the rising
edge.
24 Bits, Incl. Aux
16 Clocks
32 Clocks
00
01
10
11
1
FSYNC Output
FSF
00
01
10
11
MSTR
0
FSYNC Input
10 (bit)
000
MSB First - 32
001
011
101
111
MSB Last
LSB Last - 16
LSB Last - 18
LSB Last - 20
210 (bit)
Name
SDF
20 Bits
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
16 Bits
18 Bits
20 Bits
18 Bits
16 Bits
MSB
LSB
MSB
LSB
MSB
Left Sample
Right Sample
32 Bits
SPECIAL MODES:
* Error flags are not accurate in these modes
FSYNC is inverted FSF = 11
MSB
LSB
MSB
LSB
MSB
16 Bits
MSB
LSB
MSB
LSB
Bi-Phase Mark Data
32 Bits
LSB
VUCP
MSB
AUX
LSB
AUX
VUCP
MSB
AUX
210 MSTR
Name
SDF
110
0
MSB First - 24
010
0
MSB First - 16
010* 1
NRZ Data
100*
1
Bi-Phase Data
100
Async SCK
0
24 Bits, Incl. Aux
Figure 10. CS8413 Serial Port SDATA and FSYNC Timing
相關PDF資料
PDF描述
CS8413-CS 96 KHZ DIGITAL AUDIO RECEIVER
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CS8414-CS 96 KHZ DIGITAL AUDIO RECEIVER
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