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參數(shù)資料
| 型號： | CS8413 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 96 KHZ DIGITAL AUDIO RECEIVER |
| 中文描述： | 96 kHz的數(shù)字音頻接收器 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 646K |
| 代理商： | CS8413 |
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CS8413 CS8414
32
DS240F1
C0, Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27.
These pins are dual function with the ‘C’ bits selected when SEL is high. Channel status
information is displayed for the channel selected by CS12. C0, which is channel status bit 0,
defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of
the Ca-Ce pins. These pins are updated with the rising edge of CBL.
CS12 - Channel Select, PIN 13.
This pin is also dual function and is selected by bringing SEL high. CS12 selects sub-frame 1
(when low) or sub-frame 2 (when high) to be displayed by channel status pins C0 and Ca
through Ce.
FCK - Frequency Clock, PIN 13.
Frequency Clock input that is enabled by bringing SEL low. FCK is compared to the received
clock frequency with the value displayed on F2 through F0. Nominal input value is 6.144 MHz.
E0, E1, E2 - Error Condition, PINS 4-6.
Encoded error information that is enabled by bringing SEL low. The error codes are prioritized
and latched so that the error code displayed is the highest level of error since the last clearing
of the error pins. Clearing is accomplished by bring SEL high for more than 8 MCK cycles.
F0, F1, F2 - Frequency Reporting Bits, PINS 2-3, 27.
Encoded sample frequency information that is enabled by bringing SEL low. A proper clock on
FCK must be input for at least two thirds of a channel status block for these pins to be valid.
They are updated three times per block, starting at the block boundary. These pins are invalid
when the PLL is out of lock.
ERF - Error Flag, PIN 25.
Signals that an error has occurred while receiving the audio sample currently being read from
the serial port. Three errors cause ERF to go high: a parity or biphase coding violation during
the current sample, or an out of lock PLL receiver.
Receiver Interface
RXP, RXN - Differential Line Receivers, PINS 9, 10.
RS422 compatible line receivers.
Phase Locked Loop
MCK - Master Clock, PIN 19.
Low jitter clock output of 256 times the received sample frequency.
FILT - Filter, PIN 20.
An external 470
resistor and 0.068F capacitor is required from FILT pin to analog ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS8413-CS | 96 KHZ DIGITAL AUDIO RECEIVER |
| CS8414 | 96 KHZ DIGITAL AUDIO RECEIVER |
| CS8414-CS | 96 KHZ DIGITAL AUDIO RECEIVER |
| CSB7152-01 | 70 V, SILICON, PIN DIODE |
| CSBFB1M00J58-R1 | CERAMIC RESONATOR, 1 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8413/14/27 | 制造商:PULSE 制造商全稱:Pulse A Technitrol Company 功能描述:TELECOMMUNICATIONS PRODUCTS |
| CS8413-CS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:96 KHZ DIGITAL AUDIO RECEIVER |
| CS8413-CSR | 功能描述:音頻 DSP IC 96 kHz Digital Audio Receivers RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| CS8414 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:96 KHZ DIGITAL AUDIO RECEIVER |
| CS8414CS | 制造商:CRYS 功能描述: 制造商:The Cherry Corporation 功能描述: |
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