22
FN2969.10
November 16, 2006
FIGURE 30. WRITE TIMING
FIGURE 31. READ TIMING
Timing Waveforms (Continued)
WR
DATA
A0-A1,
CS
BUS
tWW (9)
tDW (10)
tWD (11)
tWA (8)
tAW (7)
RD
DATA
A0-A1,
CS
BUS
tRR (3)
tRA (2)
tAR (1)
VALID
(4) tRD
tDF (5)
HIGH IMPEDANCE
AC Test Circuit
AC Testing Input, Output Waveforms
R1
V1
OUTPUT FROM
DEVICE UNDER
TEST
POINT
C1
R2
(SEE NOTE)
INPUT
VIH + 0.4V
VIL - 0.4V
1.5V
VOH
VOL
OUTPUT
AC Testing: All AC Parameters tested as per test circuits. Input RISE
and FALL times are driven at 1ns/V.
TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
R2
C1
1
1.7V
523
Ω
Open
150pF
2VCC
2k
Ω
1.7k
Ω
50pF
3
1.5V
750
Ω
Open
50pF
82C55A
NOTE: Includes STRAY and JIG Capacitance