參數(shù)資料
型號: CS61881
英文描述: Octal E1 Analog Front EndLine Interface Units
中文描述: 八路素E1模擬前端底線接口單元
文件頁數(shù): 3/28頁
文件大?。?/td> 461K
代理商: CS61881
CS61881
DS451PP3
3
3. PIN DESCRIPTION ................................................................................................................. 15
3.1 Pinout - 144-Pin LQFP .................................................................................................... 15
3.2 Pinout - 160-Pin FBGA .................................................................................................... 16
3.3 Pin Descriptions ............................................................................................................... 17
4. PACKAGE DIMENSIONS ..................................................................................................... 24
5. APPLICATIONS .............................................................................................................. 26
LIST OF FIGURES
Figure 1. Signal Rise and Fall Characteristics .............................................................................. 8
Figure 2. Recovered Clock and Data Switching Characteristics ................................................... 8
Figure 3. Transmit Clock and Data Switching Characteristics ...................................................... 8
Figure 4. Mask of the Pulse at the 2048 kbps Interface ................................................................ 9
Figure 5. Test Access Port Architecture ...................................................................................... 11
Figure 6. TAP Controller State Diagram ..................................................................................... 11
Figure 7. 144-Pin LQFP Pin Description Drawing ....................................................................... 15
Figure 8. 160-Pin FBGA Pin Description Drawing ...................................................................... 16
Figure 9. Internal RX Impedance Matching ................................................................................. 26
Figure 10. External RX Impedance Matching ............................................................................. 27
LIST OF TABLES
Table 1. JTAG Instructions............................................................................................................ 13
Table 2. Boundary Scan Register................................................................................................. 14
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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