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參數(shù)資料
| 型號： | CS61881 |
| 英文描述： | Octal E1 Analog Front EndLine Interface Units |
| 中文描述： | 八路素E1模擬前端底線接口單元 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大小： | 461K |
| 代理商： | CS61881 |
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CS61881
20
DS451PP3
TPOS0 - Transmit Positive Pulse Input, LQFP Pin 37, BGA Pin N2.
TNEG0 - Transmit Negative Pulse Input, LQFP Pin 38, BGA Pin N3.
When TCLK0 is active (NRZ input mode), data on TPOS0 and TNEG0 is sampled on the
falling edge of TCLK0 and transmitted onto the line at TTIP0 and TRING0 respectively. An
input on TPOS0 results in transmission of a positive pulse; an input on TNEG0 results in
transmission of a negative pulse.
When TCLK0 is held high (RZ input mode), the pulse widths of TPOS0 and TNEG0
determine the pulse widths output on TTIP0 and TRING0. If TPOS0 and TRING0 are high at
the same time, TTIP0 and TRING0 will both be 0.
RCLK0 - Receive Clock Output, LQFP Pin 39, BGA Pin P1.
This output is the XOR of RPOS and RNEG. It can be used for external clock recovery
circuits. This output is in a high-impedance state when RPD is Low.
RPOS0 - Receive Positive Pulse Output, LQFP Pin 40, BGA Pin P2.
RNEG0 - Receive Negative Pulse Output, LQFP Pin 41, BGA Pin P3.
These pins output the RZ data recovered by the receive slicers. A positive pulse on RTIP with
respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING with respect to
RTIP generates a logic 1 on RNEG. The polarity of the output on RPOS/RNEG is selectable
with the RPS pin. Note: RPOS and RNEG will be active when the transceiver is in LOS.
RPOS/RNEG will be in a high impedance state if the RPD pin is Low.
TCLK1 - Transmit Clock Input Port 1, LQFP Pin 29, BGA Pin L1.
TPOS1 - Transmit Positive Pulse Input, LQFP Pin 30, BGA Pin L2.
TNEG1 - Transmit Negative Pulse Input, LQFP Pin 31, BGA Pin L3.
RCLK1 - Receive Clock Output, LQFP Pin 32, BGA Pin M1.
RPOS1 - Receive Positive Pulse Output, LQFP Pin 33, BGA Pin M2.
RNEG1 - Receive Negative Pulse Output, LQFP Pin 34, BGA Pin M3.
TCLK2 - Transmit Clock Input Port 2, LQFP Pin 81, BGA Pin L14.
TPOS2 - Transmit Positive Pulse Input, LQFP Pin 80, BGA Pin L13.
TNEG2 - Transmit Negative Pulse Input, LQFP Pin 79, BGA Pin L12.
RCLK2 - Receive Clock Output, LQFP Pin 78, BGA Pin M14.
RPOS2 - Receive Positive Pulse Output, LQFP Pin 77, BGA Pin M13.
RNEG2 - Receive Negative Pulse Output, LQFP Pin 76, BGA Pin M12.
TCLK3 - Transmit Clock Input Port 3, LQFP Pin 74, BGA Pin N14.
TPOS3 - Transmit Positive Pulse Input, LQFP Pin 73, BGA Pin N13.
TNEG3 - Transmit Negative Pulse Input, LQFP Pin 72, BGA Pin L2.
RCLK3 - Receive Clock Output, LQFP Pin 71, BGA Pin P14.
RPOS3 - Receive Positive Pulse Output, LQFP Pin 70, BGA Pin P13.
RNEG3 - Receive Negative Pulse Output, LQFP Pin 69, BGA Pin P12.
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相關(guān)代理商/技術(shù)參數(shù) |
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