參數(shù)資料
型號(hào)： CS61577-IP1
廠商： CIRRUS LOGIC INC
元件分類： 數(shù)字傳輸電路
英文描述： T1/E1 LINE INTERFACE
中文描述： DATACOM, PCM TRANSCEIVER, PDIP28
封裝： PLASTIC, DIP-28
文件頁(yè)數(shù)： 16/44頁(yè)
文件大?。?/td> 632K
代理商： CS61577-IP1
Serial Interface
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
host controller can be used to control operational
characteristics and monitor device status. The se-
rial port read/write timing is independent of the
system transmit and receive timing.
Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are ter-
minated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes High-Z after CS goes high
or
at the end of
the hold period of data bit D7.
An address/command byte, shown in Table 9, pre-
cedes a data register. The first bit of the
address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.
The data register, shown in Table 10, can be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver.
CS
SCLK
SDO
SDI
D6
D5
D4
D3
D2
D1
D0
D7
0
0
D7
D6
D5
D4
D3
D2
Data Input/Output
D1
D0
Address/Command Byte
0
0
0
1
0
R/W
Figure 13. Input/Output Timing
LSB, first bit
0
1
2
3
4
5
6
R/W
ADD0
ADD1
ADD2
ADD3
ADD4
-
Read/Write Select; 0 = write, 1 = read
LSB of address, Must be 0
Must be 0
Must be 0
Must be 0
Must be 1
Reserved - Must be 0
Table 9. Address/Command Byte
LSB: first bit in
0
1 clr DPM Clear Driver Performance Monitor
2
LEN0
Bit 0 - Line Length Select
3
LEN1
Bit 1 - Line Length Select
4
LEN2
Bit 2 - Line Lenght Select
5 RLOOP Remote Loopback
6
LLOOP Local Loopback
MSB: last bit in 7
TAOS
Transmit All Ones Select
NOTE: Setting 5, 6, & 7 to 101 or 111 puts the CS61577 into a
factory test mode.
clr LOS Clear Loss of Signal
Table 10. Input Data Register
CS61577
16
DS155PP2
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