參數(shù)資料
型號(hào)： CS42L51-CNZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 36/43頁(yè)
文件大小： 0K
描述： IC CODEC LOW-V 24BIT 32-QFP
標(biāo)準(zhǔn)包裝： 6,000
類(lèi)型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 98 / 98
電壓 - 電源，模擬： 1.8V，2.5V
電壓 - 電源，數(shù)字： 1.8V，2.5V
工作溫度： -10°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-QFP
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 管件
配用： 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名稱(chēng)： Q3956082
DS679F1
41
CS42L51
4.7
Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 22 on page 42. The CODEC en-
ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu-
lators and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in “Software Mode” on page 43. If a valid write sequence to the control port is not made within approximately
10 ms, the CODEC will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and
ADC_FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-
alog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK
period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1.
Hold RESET low until the power supplies are stable.
2.
Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3.
For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4.
Load the desired register settings while keeping the PDN bit set to ‘1’b.
5.
Start MCLK to the appropriate frequency, as discussed in Section 4.5.
6.
Set the PDN bit to ‘0’b.
7.
Apply LRCK,SCLK and SDIN for normal operation to begin.
8.
Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
LRCK
SCLK
MS B
LS B
MS B
LS B
L e ft C han ne l
R ig h t C h an n e l
SDIN
MSB
AOUTA / AINxA
AOUTB / AINxB
Figure 20. Left-Justified Format
LRCK
SCLK
MS B
LS B
MS B
LS B
Left C han ne l
R ig h t C han ne l
SDIN
AOUTA
AOUTB
Figure 21. Right-Justified Format (DAC only)
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