參數(shù)資料
型號： CS42L51-CNZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 21/43頁
文件大?。?/td> 0K
描述： IC CODEC LOW-V 24BIT 32-QFP
標準包裝： 6,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動態(tài)范圍，標準 ADC / DAC (db)： 98 / 98
電壓 - 電源，模擬： 1.8V，2.5V
電壓 - 電源，數(shù)字： 1.8V，2.5V
工作溫度： -10°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 32-QFP
供應商設備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 管件
配用： 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名稱： Q3956082
28
DS679F1
CS42L51
4.3
Analog Inputs
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig-
nals, allowing various gain and signal adjustments for each channel.
4.3.1
Digital Code, Offset & DC Measurement
The ADC output data is in two’s complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.
To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
The CODEC may be used to measure DC voltages by disabling the high-pass filter for the designated
channel. DC levels are measured relative to VQ and will be decoded as positive two’s complement binary
numbers above VQ and negative two’s complement binary numbers below VQ.
Software
Controls:
Multibit
Oversampling
ADC
AIN3A/ MICIN1
MICA_BOOST
Attenuator
ALC
PGAA_VOL[5:0]
ADC_SNGVOL
0/-96dB
1dB steps
ADCA_ATT[7:0]
ADCA_HPF ENABLE
ADCA_HPF FREEZE
PDN_ADCA
ADCA_MUTE
SOFTA
ALC_ENA
ALCB_SRDIS
ALCB_ZCDIS
PDN_MICA
MICBIAS
PDN_MICBIAS
MICBIAS_LVL[1:0]
PC
M
Se
ri
a
l
In
te
rf
ac
e
MICBIAS_SEL
TO SIGNAL PROCESSING
ENGINE (SPE)
INV_ADCA
ALC_ARATE[5:0]
ALC_RRATE[5:0]
MAX[2:0]
MIN[2:0]
ALC_ENB
ALCA_SRDIS
ALCA_ZCDIS
MUX
AIN1A
AIN2A
PGA
+16/
32 dB
AINA_MUX[1:0]
PDN_PGAA
+12/-3dB
0.5dB steps
SOFTA
ZCROSSA
Multibit
Oversampling
ADC
AIN3B/ MICIN2/
MICBIAS
MICB_BOOST
PGAB_VOL[5:0]
ADC_SNGVOL
0/-96dB
1dB steps
ADCB_ATT[7:0]
ADCB_HPF ENABLE
ADCB_HPF FREEZE
PDN_ADCB
ADCB_MUTE
SOFTB
PDN_MICB
INV_ADCB
MUX
AIN1B
AIN2B/MICBIAS
PGA
+16/
32 dB
AINB_MUX[1:0]
PDN_PGAB
+12/-3dB
0.5dB steps
SOFTB
ZCROSSB
Noise Gate
NG_ALL
NG_EN
THRESH[3:0]
NGDELAY[1:0]
Attenuator
Σ
MUX
MICMIX
MUX
FROM SIGNAL
PROCESSING ENGINE
(SPE)
DIGMIX
+20dB
Digital
Boost
ADCA_DBOOST
+20dB
Digital
Boost
ADCB_DBOOST
Figure 8. Analog Input Architecture
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