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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | CS4207-CNZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/77闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CODEC AUD HDPN AMP COMM 48QFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 429 |
| 椤炲瀷锛� | 闊抽牷绶ㄨВ纰煎櫒 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 24 b |
| ADC / DAC 鏁�(sh霉)閲忥細 | 2 / 3 |
| 涓夎绌嶅垎瑾�(di脿o)璁婏細 | 鏄� |
| 鍕�(d貌ng)鎱�(t脿i)鑼冨湇锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db)锛� | 105 / 110 |
| 闆诲 - 闆绘簮锛屾ā鎿細 | 2.97 V ~ 5.25 V |
| 闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 | 2.97 V ~ 5.25 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-QFN |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-QFN-EP锛�6x6锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | 598-1796 |
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22
DS880F4
CS4207
DIGITAL MICROPHONE INTERFACE CHARACTERISTICS
Test conditions: Inputs: Logic 0 = GND = 0 V, Logic 1 = VL_IF; TA = +25 C; CLOAD = 30 pF.
Notes:
12. The output clock frequency will follow the Bit Clock (BITCLK) frequency divided by 8 or 12, depending on
the sample rate of the ADC. Any deviation of the Bit Clock source from the nominal supported rates will be
directly imparted to the output clock rate by the same factor (e.g. +100 ppm offset in the frequency of BIT-
CLK will become a +100 ppm offset in DMIC_SCL). For the nominal value of T_cyc reference HDA024-A
(see Note 4 in 鈥淩eferences鈥� on page 147).
13. Rise and fall times are measured from 0.1 VL_IF to 0.9 VL_IF.
Figure 7. Digital MIC Interface Timing
Parameters
Symbol
Min
Typ
Max
Units
DMIC_SCL Period (FsADC >= 44.1 kHz)
tP
-
8 T_cyc
-
ns
DMIC_SCL Period (FsADC <= 32.0 kHz)
tP
-
12 T_cyc
-
ns
DMIC_SCL Duty Cycle
-
45
-
55
%
DMIC_SCL Rise Time
tr
-
10
ns
DMIC_SCL Fall Time
tf
-
10
ns
DMIC_SDA Setup Time Before DMIC_SCL Rising Edge
ts(SD-CLKR)
40
-
ns
DMIC_SDA Hold Time After DMIC_SCL Rising Edge
th(CLKR-SD)
5-
-
ns
DMIC_SDA Setup Time Before DMIC_SCL Falling Edge
ts(SD-CLKF)
40
-
ns
DMIC_SDA Hold Time After DMIC_SCL Falling Edge
th(CLKF-SD)
6-
-
ns
DMIC_SCL
DMIC_SDA
th(CLKR-SD)
tP
tr
tf
th(CLKF-SD)
ts(SD-CLKR)
ts(SD-CLKF)
Right
(B, DATA2)
Channel Data
Left
(A, DATA1)
Channel Data
Left
(A, DATA1)
Channel Data
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-B40-IW-B1 | CONVERTER MOD DC/DC 5V 100W |
| VE-B1X-IW-B1 | CONVERTER MOD DC/DC 5.2V 100W |
| VE-B10-IX-B1 | CONVERTER MOD DC/DC 5V 75W |
| VE-B10-IW-B1 | CONVERTER MOD DC/DC 5V 100W |
| VE-B0J-IX-B1 | CONVERTER MOD DC/DC 36V 75W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS4207-CNZ/C1 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp |
| CS4207-CNZR | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| CS4207-CNZR/C1 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp |
| CS4207-DNZ | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| CS4207-DNZR | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
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