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鍨嬭櫉(h脿o)锛� CS4207-CNZ
寤犲晢锛� Cirrus Logic Inc
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鎻忚堪锛� IC CODEC AUD HDPN AMP COMM 48QFN
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鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 598-1796
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2
DS880F4
CS4207
Digital Audio Interface Receiver
Complete EIAJ CP1201, IEC 60958, S/PDIF
Compatible Receiver
32 kHz to 192 kHz Sample Rate Range
Automatic Detection of Compressed Audio
Streams
Integrated Sample Rate Converter
鈥�
128 dB Dynamic Range
鈥�
-120 dB THD+N
鈥�
Supports Sample Rates up to 192 kHz
鈥�
1:1 Input/Output Sample Rate Ratios
Digital Audio Interface Transmitters
Two Independent EIAJ CP1201, IEC-60958,
S/PDIF Compatible Transmitters
32 kHz to 192 kHz Sample Rate Range
System Features
Very Low D3 Power Dissipation of <7 mW
鈥�
Jack Detect Active in D3
鈥�
HDA BITCLK Not Required for D3 State
Jack Detect Does Not Require HDA Bus
BITCLK
All Configuration Settings are Preserved in D3
State
Pop/Click Suppression in State Transitions
Detects Wake Event and Generates Power
State Change Request when HDA Bus
Controller is in D3
Variable Power Supplies
鈥�
1.5 V to 1.8 V Digital Core Voltage
鈥�
3.3 V to 5.0 V Analog Core Voltage
鈥�
3.3 V to 5.0 V Headphone Drivers
鈥�
1.5 V to 3.3 V HD Bus Interface Logic
鈥�
3.3 V Interface Logic levels for GPIO,
S/PDIF, and Digital Mic
Individual Power-down Managed
鈥�
ADCs, DACs, PGAs, Headphone Driver,
S/PDIF Receiver, and Transmitters
General Description
The CS4207 is a highly integrated multi-channel low-
power HD Audio Codec featuring 192 kHz DACs,
96 kHz ADCs, 192 kHz S/PDIF Transmitters and Re-
ceiver, Microphone pre-amp and bias voltage, and a
ground centered Headphone driver. Based on multi-bit,
delta-sigma modulation, it allows infinite sample rate
adjustment between 32 kHz and 192 kHz.
The ADC input path allows control of a number of fea-
tures. The microphone input path includes a selectable
programmable-gain pre-amplifier stage and a low-noise
MIC bias voltage supply. A PGA is available for line and
microphone inputs and provides analog gain with soft
ramp and zero cross transitions. The ADC also features
an additional digital volume attenuator with soft ramp
transitions.
The stereo headphone amplifier is powered from a sep-
arate internally generated positive supply, with an
integrated charge pump providing a negative supply.
This allows a ground-centered analog output with a
wide signal swing and eliminates external DC-blocking
capacitors.
The integrated digital audio interface receiver and trans-
mitters utilize a 24-bit, high-performance, monolithic
CMOS stereo asynchronous sample rate converter to
clock align the PCM samples to/from the S/PDIF inter-
faces. Auto detection of non-PCM encoded data
disables the sample rate conversion to preserve bit ac-
curacy of the data.
In addition to its many features, the CS4207 operates
from a low-voltage analog and digital core, making this
part ideal for portable systems that require low power
consumption in a minimal amount of space.
The CS4207 is available in a 48-pin WQFN package in
both Automotive (-40掳C to +105掳C) and Commercial
(-40掳C to +85掳C) grades. The CS4207 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions. Please refer to 鈥淥r-
information.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
CS4207-CNZ/C1 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
CS4207-CNZR 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4207-CNZR/C1 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
CS4207-DNZ 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4207-DNZR 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel