參數(shù)資料
型號(hào): CS4202-JQZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 4/66頁(yè)
文件大小: 0K
描述: IC AC 97 W/HEADPHONE AMP 48TQFP
標(biāo)準(zhǔn)包裝: 250
類(lèi)型: 音頻編解碼器 '97
數(shù)據(jù)接口: 串行
分辨率(位): 18,20 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 90 / 90
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(9x9)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 754 (CN2011-ZH PDF)
其它名稱: 598-1181
Micrel, Inc.
MIC3001
August 2004
12
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Control and Status I/O Timing, TXFAULT, TXDISABLE, RSIN, RSOUT, and RXLOS
tOFF
TXDISABLE Assert Time
From input asserted to optical output
at 10% of nominal, CCOMP = 10nF.
10
s
tON
TXDISABLE De-assert Time
From input de-asserted to optical
output at 90% of nominal, CCOMP =
10nF.
1
ms
tINIT
Initialization Time
From power on or transmitter enabled
to optical output at 90% of nominal
and TX_FAULT de-asserted.(4)
300
ms
tINIT2
Power-on Initialization Time
From power on to APC loop enabled.
200
ms
tFAULT
TXFAULT Assert Time
From fault condition to TXFAULT
assertion.(4)
95
s
tRESET
Fault Reset Time
Length of time TXDISABLE must be
asserted to reset fault condition.
10
s
tLOSS_ON
RXLOS Assert Time
From loss of signal to RXLOS
asserted.
95
s
tLOSS_OFF
RXLOS De-assert Time
From signal acquisition to LOS de-
asserted.
100
s
tDATA
Analog Parameter Data Ready
From power on to valid analog
parameter data available.(4)
400
ms
tPROP_IN
TXFAULT, TXDISABLE, RXLOS,
RSIN Input Propagation Time
Time from input change to
corresponding internal register bit set
or cleared.(4)
1
s
tPROP_OUT
TXFAULT, RSOUT, /INT Output
Propagation Time
From an internal register bit set or
cleared to corresponding output
change.(4)
1
s
Fault Comparators
φ
FLTTMR
Fault Suppression Timer Clock
Period
Note 4
0.475
0.5
0.525
ms
Accuracy
-3
+3
%/F.S.
tREJECT
Glitch Rejection
Maximum length pulse that will not
cause output to change state.(4)
4.5
s
VSAT
Saturation Detection Threshold
High level
95
%VDDA
Low level
5
%VDDA
Power-On Hour Meter
Timebase Accuracy
0°C
≤ T
A ≤ +70°C
(4)
+5
-5
%
–40°C
≤ T
A ≤ +105°C
+10
-10
%
Resolution
Note 4
10
hours
Non-Volatile (FLASH) Memory
tWR
Write Cycle Time(7)
From STOP of a one to four-byte write
transaction.(4)
13
ms
Data Retention
100
years
Endurance
Minimum Permitted Number
Write Cycles
10,000
cycles
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