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參數(shù)資料
| 型號： | CS3842AGDR14 |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, PDSO14 |
| 封裝： | SO-14 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 156K |
| 代理商： | CS3842AGDR14 |
5
CS2842A/3843A
SERIES
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator com-
ponents.
Setting the Oscillator
Oscillator timing capacitor, CT, is charged by VREF through
RT and discharged by an internal current source. During
the discharge time, the internal clock signal blanks out the
output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times
are determined by the formula:
tc = RTCT ln
td = RTCT ln
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA
tc ≈ 0.5534RTCT
td = RTCT ln
The frequency and maximum duty cycle can be deter-
mined using the Typical Performance Characteristic
graphs.
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd pin in a sin-
gle point ground.
The transistor and 5k potentiometer, shown in the test
circuit, are used to sample the oscillator waveform and
apply an adjustable ramp to Sense.
)
2.3 - 0.0083 RT
4.0 - 0.0083 RT
(
)
VREF - IdRT - Vlower
VREF - IdRT - Vupper
(
)
VREF - Vlower
VREF - Vupper
(
VREF
OSC
Gnd
RT
CT
Circuit Description: continued
VOSC
Internal Clock
LARGE RT (≈10k)
VREF
Internal Clock
SMALL RT (≈700)
Sawtooth Mode
Triangular Mode
Vupper
Vlower
tc
td
VCC
IOUT
VOUT
Switch
Current
EA Output
VOSC
OSC
RESET
Figure 2: Timing Diagram for key CS2841B parameters
Figure 3: Oscillator Timing Network and parameters
Timing parameters
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