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參數(shù)資料
| 型號： | EPM1270 |
| 廠商： | Altera Corporation |
| 英文描述： | JTAG & In-System Programmability |
| 中文描述： | JTAG接口 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 103K |
| 代理商： | EPM1270 |
3–2
MAX II Device Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
June 2004
IEEE Std. 1149.1 (JTAG) Boundary Scan Support
HIGHZ
(1)
00 0000 1011
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while tri-stating all of the I/O
pins.
CLAMP
(1)
00 0000 1010
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while holding I/O pins to a
state defined by the data in the boundary-scan register.
USER0
00 0000 1100
This instruction allows the user to define their own scan chain
between
TDI
and
TDO
in the MAX II logic array. This
instruction is also used for custom logic and JTAG interfaces.
USER1
00 0000 1110
This instruction allows the user to define their own scan chain
between
TDI
and
TDO
in the MAX II logic array. This
instruction is also used for custom logic and JTAG interfaces.
IEEE 1532 instructions
(2)
IEEE 1532 ISC instructions used when programming a MAX II
device via the JTAG port.
Notes to
Table 3–1
:
(1)
HIGHZ
,
CLAMP
, and
EXTEST
instructions do not disable weak pull-up resistors or bus hold features.
(2)
These instructions are shown in the 1532 BSDL files, which will be posted on the Altera
web site at
www.altera.com
when they are available.
Table 3–1. MAX II JTAG Instructions (Part 2 of 2)
JTAG Instruction
Instruction Code
Description
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PDF描述 |
|---|---|
| EPM2210 | JTAG & In-System Programmability |
| EPM240 | JTAG & In-System Programmability |
| EPM570 | JTAG & In-System Programmability |
| EPM3032A | Programmable Logic Device Family |
| EPM3064A | Programmable Logic Device Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM1270100C5N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m, |
| EPM1270F100A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM1270F100C | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM1270F100I | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM1270F256A5N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 980 Macro 212 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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