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參數(shù)資料
| 型號(hào)： | COP8CBR9HLQ8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 62/111頁 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 44LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 37 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-WFQFN 裸露焊盤 |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | *COP8CBR9HLQ8 COP8CBR9HLQ8CT |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.12.4.1.4 HALT Exit Using Multi-Input Wake-up
The device can be brought out of the HALT mode by a transition received on one of the available Wake-
up pins. The pins used and the types of transitions sensed on the Multi-input pins are software
programmable. For information on programming and using the Multi-Input Wake-up feature, refer to Multi-
A start-up delay is required between the device wake-up and the execution of program instructions. The
start-up delay is mandatory, and is implemented whether or not the CLKDLY bit is set. This is because all
crystal oscillators and resonators require some time to reach a stable frequency and full operating
amplitude.
If the start-up delay is used, the IDLE Timer (Timer T0) provides a fixed delay from the time the clock is
enabled to the time the program execution begins. Upon exit from the HALT mode, the IDLE Timer is
enabled with a starting value of 256 and is decremented with each instruction cycle using the high speed
clock. (The instruction clock runs at one-fifth the frequency of the high speed oscillatory.) An internal
Schmitt trigger connected to the on-chip CKI inverter ensures that the IDLE Timer is clocked only when
the high speed oscillator has a large enough amplitude. (The Schmitt trigger is not part of the oscillator
closed loop.) When the IDLE Timer underflows, the clock signals are enabled on the chip, allowing
program execution to proceed. Thus, the delay is equal to 256 instruction cycles. After exiting HALT, the
Idle Timer will return to being clocked by the low speed clock.
NOTE
To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the
instruction in the application program used for entering the HALT mode should be followed
by two consecutive NOP (no-operation) instructions.
5.12.4.1.5 Options
This device has two options associated with the HALT mode. The first option enables the HALT mode
feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option
will cause the microcontroller to ignore any attempts to HALT the device under software control. See
Option Register for more details on this option bit.
5.12.4.2 Dual Clock Idle Mode
In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with
the HALT mode. However, both oscillators, IDLE Timer (Timer T0), and Clock Monitor continue to operate,
allowing real time to be maintained. The Idle Timer is clocked by the low speed clock. The device remains
idle for a selected amount of time up to 1 second, and then automatically exits the IDLE mode and returns
to normal program execution using the high speed clock.
The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G
data register).
The IDLE Timer window is selectable from one of five values, 0.125 seconds, 0.25 seconds, 0.5 seconds,
1 second and 2 seconds. Selection of this value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state.
The IDLE Timer runs continuously at the low speed clock rate, whether or not the device is in the IDLE
mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an
interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer
interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However,
the instruction which was started as the part entered the IDLE mode is completed before the interrupt is
serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must
reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode.
As with the HALT mode, this device can also be returned to normal operation with a Multi-Input Wake-up
input.
54
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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