
COP410L/411L Instruction Set
Table II is a symbol table providing internal architecture, in-
struction operand and operational symbols used in the in-
struction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP410L/411L instruction set.
TABLE II. COP410L/411L Instruction Set Table Symbols
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
A
B
Br
Bd
C
D
EN
G
L
M
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by B
Register
9-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register B
4-bit Shift Register and Counter
Logic-Controlled Clock Output
PC
Q
SA
SB
SIO
SK
Symbol
Definition
INSTRUCTION OPERAND SYMBOLS
d
r
4-bit Operand Field, 0–15 binary (RAM Digit Select)
2-bit Operand Field, 0–3 binary (RAM Register
Select)
9-bit Operand Field, 0–511 binary (ROM Address)
4-bit Operand Field, 0–15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
a
y
OPERATIONAL SYMBOLS
a
b
x
Y
e
A
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one’s complement of A
Exclusive-OR
Range of values
Z
:
TABLE III. COP410L/411L Instruction Set
Hex
Code
Machine
Language Code
(Binary)
à
0011
0000
à
à
0011
à
0001
à
à
0101
à
à
0000
à
0000
à
à
0100
à
0000
à
à
0100
à
0100
à
à
0011
à
0010
à
à
0010
à
0010
à
à
0000
à
0010
à
Mnemonic
Operand
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
A
a
C
RAM(B)
x
A
Carry
x
C
Carry
Add with Carry, Skip on
Carry
ADD
31
A
a
RAM(B)
x
A
None
Add RAM to A
AISC
y
5–
y
à
A
a
y
x
A
Carry
Add Immediate, Skip on
Carry (y
i
0)
CLRA
00
0
x
A
None
Clear A
COMP
40
A
x
A
None
One’s complement of A to A
NOP
44
None
None
No Operation
RC
32
‘‘0’’
x
C
None
Reset C
SC
22
‘‘1’’
x
C
None
Set C
XOR
02
A
Z
RAM(B)
x
A
None
Exclusive-OR RAM with A
14