參數(shù)資料
型號: COP310L
廠商: National Semiconductor Corporation
英文描述: Single-Chip N-Channel Microcontrollers
中文描述: 單芯片N溝道微控制器
文件頁數(shù): 11/20頁
文件大?。?/td> 331K
代理商: COP310L
L-Bus Considerations
False states may be generated on L
0
–L
7
during the execu-
tion of the CAMQ instruction. The L-ports should not be
used as clocks for edge sensitive devices such as flip-flops,
counters, shift registers, etc. the following short program
that illustrates this situation.
START:
CLRA
;ENABLE THE Q
LEI
4
;REGISTER TO L LINES
LBI
TEST
STII 3
AISC 12
LOOP:
LBI
TEST
;LOAD Q WITH X’C3
CAMQ
JP
LOOP
In this program the internal Q register is enabled onto the L
lines and a steady bit pattern of logic highs is output on L
0
,
L
1
, L
6
, L
7
, and logic lows on L
2
–L
5
via the two-byte CAMQ
instruction. Timing constraints on the device are such that
the Q register may be temporarily loaded with the second
byte of the CAMQ opcode (X
ê
3C) prior to receiving the valid
data pattern. If this occurs, the opcode will ripple onto the L
lines and cause negative-going glitches on L
0
, L
1
, L
6
, L
7
,
and positive glitches on L
2
–L
5
. Glitch durations are under
2
m
s, although the exact value may vary due to data pat-
terns, processing parameters, and L line loading. These
false states are peculiar only to the CAMQ instruction and
the L lines.
Typical Performance Characteristics
Input Current RESET, SI
Off by Software
L7 when Output Programmed
Input Current for L0 through
Output Configuration
Source Current for Standard
Configuration
and SK in Push-Pull
Source Current for SO
(High Current Option)
L7 in TRI-STATE Configuration
Source Current for L0 through
(Low Current Option)
L7 in TRI-STATE Configuration
Source Current for L0 through
TL/DD/6919–18
FIGURE 8a. COP410L/COP411L I/O DC Current Characteristics
11
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