參數(shù)資料
型號(hào)： CMOD232+
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 0K
描述： EVAL SYSTEM FOR MAX9850
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
General-Purpose Register
GPIO Output Mode Control (GM(1:0))
00 = GPIO outputs low.
01 = GPIO is high impedance.
10 = GPIO outputs low and the ALERT output pulse
function is enabled.
11 = GPIO is high impedance and the ALERT output
pulse function is enabled.
GM(1:0) programs the GPIO output state and enables
or disables the ALERT output pulse function. The open-
drain GPIO output can be programmed to output static
high or a low. GPIO can also be programmed to pulse
to the opposite output level than the programmed out-
put state when an alert occurs. An alert occurs when
ALERT sets to 1 in the status A register. GM(1:0) has no
function when GPIO is configured as an input.
GPIO Direction (GPD)
1 = Configure GPIO as an open-drain output.
0 = Configure GPIO as an input.
The state of GPD determines whether GPIO is an input
or an output.
Debounce Delay Control (DBDEL(1:0))
00 = HPS debounce delay disabled.
01 = HPS debounce delay is a nominal 200ms.
10 = HPS debounce delay is a nominal 400ms.
11 = HPS debounce delay is a nominal 800ms.
DBDEL(1:0) controls the length of HPS debounce time.
The debounce time is derived from the charge-pump
clock.
Mono Mode Enable (MONO)
1 = Enable mono mode.
0 = Disable mono mode, headphone outputs in stereo
mode.
Set MONO = 1 to force the headphone outputs to mono
mode. The stereo input signal is summed to one chan-
nel. The summed signal is output on the left headphone
output (HPL).
Zero-Detect Enable (ZDEN)
1 = Enables the zero-detect function.
0 = Disables the zero-detect function.
Volume changes, headphone output muting, and enter-
ing/exiting shutdown occur only on the zero crossing of
the audio signal when ZDEN = 1. For optimum perfor-
mance, set SR(1:0) to 01.
Interrupt Enable Register
Note: Any of the below interrupts can be configured to
trigger a hardware interrupt through GPIO. Program
GPD and GM(1:0) in the general-purpose register to
enable the ALERT output pulse function.
SGPIO Interrupt Enable (ISGPIO)
1 = A state change on SGPIO, when GPIO is an input,
will cause ALERT to set to 1.
0 = A state change on SGPIO, when GPIO is an input,
will not cause ALERT to set.
ISGPIO = 1 configures the MAX9850 to set ALERT = 1
when SGPIO changes state. The interrupt may only be
enabled when GPIO is an input.
PLL Lock Interrupt Enable (ILCK)
1 = A state change on LCK will cause ALERT to set to 1.
0 = A state change on LCK will not cause ALERT to set.
ILCK = 1 configures the MAX9850 to set ALERT = 1
when the DAC’s internal PLL loses or achieves frequen-
cy lock with LRCLK. Program GM(1:0), while GPD = 1,
to configure GPIO as a hardware interrupt to alert a C
when LCK changes state.
SHPS Interrupt Enable (ISHPS)
1 = A state change on SHPS will cause ALERT to set to 1.
0 = A state change on SHPS will not cause ALERT to set.
ISHPS = 1 configures the MAX9850 to set ALERT = 1
when SHPS changes state.
Volume at Minimum Interrupt Enable (IVMN)
1 = A state change on VMN will cause ALERT to set to 1.
0 = A state change on VMN will not cause ALERT to set.
IVMN = 1 configures the MAX9850 to set ALERT = 1
when the headphone amplifier is programmed to and
reaches its minimum output volume. Program GM(1:0),
while GPD = 1, to configure GPIO as a hardware interrupt
to alert a C when the headphone output volume is pro-
grammed to and reaches its minimum volume.
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________
25
Table 14. General Purpose (0x3)
Read/Write, Bit Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
GM(1:0)
GPD
DBDEL(1:0)
MONO
0
ZDEN
Table 15. Interrupt Enable (0x4)
Read/Write, Bit Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
0
ISGPIO
ILCK
ISHPS
IVMN
00
IIOH
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