參數(shù)資料
型號： CLRC63201T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Multiple protocol contactless reader IC (MIFARE-I-CODE1)
封裝： CLRC63201T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;
文件頁數(shù)： 56/126頁
文件大?。?/td> 719K
代理商： CLRC63201T
CLRC632_35
NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 10 November 2009
073935
35 of 126
NXP Semiconductors
CLRC632
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90
° between them. Both resulting subcarrier signals are amplied, ltered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1 Receiver circuit block diagram
Figure 12 shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see Section 9.10.2.1 on page 35).
The demodulated signal is amplied by an adjustable amplier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in Figure 12. One
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
9.10.2 Receiver operation
In general, the default settings programmed in the StartUp initialization le are suitable for
use with the CLRC632 to MIFARE card data communication. However, in some
environments specic user settings will achieve better performance.
9.10.2.1
Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
anda90
° phase-shifted quadrature signal (Q-clock). To achieve the optimum demodulator
performance, the Q-clock and the I-clock must be phase-shifted by 90
°. After the reset
phase, a calibration procedure is automatically performed.
Fig 12. Receiver circuit block diagram
001aak615
ClkQDelay[4:0]
ClkQCalib
ClkQ180Deg
BitPhase[7:0]
CORRELATION
CIRCUITRY
EVALUATION
AND
DIGITIZER
CIRCUITRY
MinLevel[3:0]
CollLevel[3:0]
RxWait[7:0]
RcvClkSell
s_valid
s_data
s_coll
s_clock
Gain[1:0]
to
TestAnaOutSel
clock
I TO Q
CONVERSION
I-clock
Q-clock
13.56 MHz
DEMODULATOR
RX
VCorrDI
VCorrNI
VCorrDQ
VCorrNQ
VEvalR
VEvalL
VRxFollQ
VRxFollI
VRxAmpI
VRxAmpQ
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參數(shù)描述
CLRC63201T/0FE 制造商:NXP Semiconductors 功能描述:
CLRC63201T/0FE,112 功能描述:RFID應(yīng)答器 I.CODE HS READER RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
CLRC63201T/0FE,118 制造商:NXP Semiconductors 功能描述:Interface Misc
CLRC63201T/0FE112 制造商:NXP Semiconductors 功能描述:CNTCLESS RC 5V ISO14443 + ISO15693
CLRC663 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC
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