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參數(shù)資料
| 型號： | CL10K50SQC208-1X |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 178K |
| 代理商： | CL10K50SQC208-1X |
LIBERATOR CL10K30A
Page 9
AC Electrical Specifications
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Unit
tIOD
IOE Register Data Delay
2.2
2.6
3.4
ns
tIOC
IOE Register Control Signal Delay
0.3
0.5
ns
tIOCO
IOE Register Clock to Output Delay
0.2
0.3
ns
tIOCOMB IOE Combinatorial Delay
0.5
0.6
0.8
ns
tIOSU
IOE Register Setup Time Before Clock
1.4
1.7
2.2
ns
tIOH
IOE Register Hold Time After Clock
0.9
1.1
1.4
ns
tIOCLR
IOE Register Clear Delay
0.7
0.8
1.0
ns
tZX
Output Buffer Disable Delay[6]
2.2
2.6
3.4
ns
tINREG
IOE Input Pad and Buffer to IOE Register
Delay
4.4
5.2
6.8
ns
tIOFD
IOE Register Feedback Delay
3.8
4.5
5.9
ns
tINCOMB
IOE Input Pad and Buffer to Interconnect
Delay
3.8
4.5
5.9
ns
Speed: -2
Speed: -3
tOD1
Output Buffer and Pad Delay
Slow Slew Rate = off, VCCIO = VCCINT
2.2
2.9
Speed: -1
ns
tOD3
Output Duffer and Pad Delay
Slow Slew Rate = on
8.2
10.8
ns
1.9
tZX1
Output Buffer Disable Delay
Slow Slew Rate = off, VCCIO = VCCINT[6]
2.6
3.4
ns
11.3
ns
tZX3
Output Buffer Disable Delay
Slow Slew Rate = on[6]
8.6
7.3
7.0
2.2
10KA tbl 06C
tOD2
Output Buffer and Pad Delay
Slow Slew Rate = off, VCCIO = Low Voltage
4.8
5.6
7.3
ns
tZX2
Output Buffer Disable Delay
Slow Slew Rate = off, VCCIO = Low
Voltage[6]
5.1
6.0
7.8
I/O Element Timing Parameters [5]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL10K50SQC208-2 | FPGA |
| CL10K50SQC208-2X | FPGA |
| CL10K50SQC208-3 | FPGA |
| CL10K50SQC240-1 | FPGA |
| CL10K50SQC240-1X | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL10K50SQC208-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC208-2X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC208-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC240-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC240-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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