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參數(shù)資料
| 型號(hào)： | CL10K50SQC208-2 |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | CL10K50SQC208-2 |
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Parameter
CL10K30A
CL10K50V
CL10K100A
Typical Gates
(Logic and RAM)
30,000
50,000
100,000
Maximum System Gates
69,000
116,000
158,000
Logic Elements
1,728
2,880
4,992
Logic Blocks
216
360
624
Embedded Array Blocks
6
10
12
Total RAM Bits
12,288
20,480
24,576
Max User I/O Pins
189
274
406
Speed Grades
-1, -2, -3
-1, -2, -3, -4
-1, -2, -3
10KA tbl 01A
Packages
144-pin TQFP
208-pin PQFP
240-pin PQFP
256-pin FBGA
240-pin PQFP
240-pin RQFP
356-pin SBGA
240-pin PQFP
240-pin RQFP
356-pin SBGA
484-pin FBGA
600-pin SBGA
March 2001
Page 1
u Fully Compatible To The Altera FLEX 10KA Family
u Prototype Your System With Altera FPGAs
u Seamlessly Migrate Production To Clear Logic
u No ASIC Engineering, No NRE, And No Test Vector
Development
u Very Fast, Dense Signal Routing Using Vertical Link
Interconnect
u "Gate Array" Option Eliminates Configuration EPROMs
u Fabricated Using 0.35 Micron CMOS Process
u Very Low Power Consumption (Active And Standby)
u High Density
- 30,000 Usable Gates
- 1,728 Logic Elements
- 12,288 RAM Bits
- 189 Maximum User I/O Pins
CL10KA Product Family Overview
LIBERATOR
CL10K30A
Key Features
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL10K50SQC208-2X | FPGA |
| CL10K50SQC208-3 | FPGA |
| CL10K50SQC240-1 | FPGA |
| CL10K50SQC240-1X | FPGA |
| CL10K50SQC240-2 | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL10K50SQC208-2X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC208-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC240-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC240-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC240-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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