- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378446 > CH7013A-V (Electronic Theatre Controls, Inc.) Digital PC to TV Encoder PDF資料下載
參數(shù)資料
| 型號： | CH7013A-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder |
| 中文描述： | 數(shù)碼電腦電視編碼器 |
| 文件頁數(shù)： | 33/46頁 |
| 文件大小： | 249K |
| 代理商： | CH7013A-V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
CHRONTEL
CH7013A
201-0000-041 Rev. 1.0, 6/14/2000
33
Register Descriptions
(continued)
Vertical Position Register
Symbol: VPR
Address: 0BH
Bits: 8
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically cen-
tered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync)
used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses).
Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen.
Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one
TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is
the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number
should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When pan-
ning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next
step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a
number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
Sync Polarity Register
Symbol: SPR
Address: 0DH
Bits: 4
This register provides selection of the synchronization signal input to, or output from, the CH7013A.
HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low, and a
value of one means the horizontal sync is active high.
VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low, and a value of
one means the vertical sync is active high.
SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7013A. A
value of one means that H and V sync are output from the CH7013A.
DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from
the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes
on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
Note:
When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical
sync will use a fixed pulse width of 2 lines.
Bit:
Symbol:
Type:
Default:
7
VP7
6
VP6
5
VP5
4
VP4
3
VP3
2
VP2
1
VP1
0
VP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit:
Symbol:
Type:
Default:
7
6
5
4
3
DES
2
SYO
1
VSP
0
HSP
R/W
R/W
R/W
R/W
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CHB1143 | CHB1143 |
| CHF12545CBF | 500 W Power RF Flanged Chip Termination |
| CHF12545CBF500L | 500 W Power RF Flanged Chip Termination |
| CHF12545CBF500R | 500 W Power RF Flanged Chip Termination |
| CHF190104CBF | 800 W Power RF Flanged Chip Termination/Resistor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-DF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-DF-TR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-D-TR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。