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參數(shù)資料
| 型號(hào)： | CG7C324-A30JC |
| 英文描述： | UV-Erasable/OTP PLD |
| 中文描述： | UV-Erasable/OTP可編程邏輯器件 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 326K |
| 代理商： | CG7C324-A30JC |
PLDC20RA10
7
Switching Characteristics
Over the Operating Range
[3, 7, 8]
Parameter
t
PD
Description
Commercial
–
15
Min.
Max.
15
Military
–
25
Min.
Unit
ns
–
20
–
20
–
35
Min.
Max.
20
Min.
Max.
20
Max.
25
Min.
Max.
35
Input or Feedback to
Non-Registered Output
Input to Output Enable
Input to Output
Disable
Pin 13 to Output
Enable
Pin 13 to Output
Disable
Clock to Output
Input or Feedback
Set-Up Time
Hold Time
Clock Period
(t
SU
+ t
CO)
Clock Width HIGH
[5]
Clock Width LOW
[5]
Maximum Frequency
(1/t
P
)
[5]
Input of Asynchronous
Set to Registered Output
Input of Asynchronous
Reset to Registered
Output
Asynchronous Reset
Width
[5]
Asynchronous S-Width
[5]
Asynchronous Set/
Reset Recovery Time
Preload Pulse Width
Preload Set-Up Time
Preload Hold Time
t
EA
t
ER
15
15
20
20
20
20
30
30
35
35
ns
ns
t
PZX
12
15
15
20
25
ns
t
PXZ
12
15
15
20
25
ns
t
CO
t
SU
15
20
20
25
35
ns
ns
7
10
10
15
20
t
H
t
P
3
22
5
30
3
30
5
40
5
55
ns
ns
t
WH
t
WL
f
MAX
10
10
45.5
13
13
33.3
12
12
33.3
18
18
25.0
25
25
18.1
ns
ns
MHz
t
S
15
20
20
25
40
ns
t
R
15
20
20
25
40
ns
t
ARW
15
20
20
25
25
ns
t
ASW
t
AR
15
10
20
12
20
12
25
15
25
20
ns
ns
t
WP
t
SUP
t
HP
Notes:
7.
8.
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
ns
ns
ns
Part (a) of AC Test Loads was used for all parameters except t
, t
, t
and t
, which use part (b).
The parameters t
and t
are measured as the delay from the input disable logic threshold transition to V
- 0.5 V for an enabled HIGH output or V
OL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
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